IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 121

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–15. Multiplexed Configuration Register Information Available on tl_cfg_ctl (Part 2 of 2)
Table 5–16. Configuration Space Register Descriptions (Part 1 of 3)
December 2010 Altera Corporation
F
Note to
(1) Items in
(2) This field is encoded as specified in Section 7.8.4 of the
Register
cfg_devcsr
cfg_dev2csr
cfg_slotcsr
cfg_linkcsr,
cfg_link2csr
cfg_prmcsr
Address
Table
blue
5–15:
are only available for root ports.
Width
32
16
32
16
31:24
Table 5–16
Table
5–15.
Dir
O
O
O
O
16’h0000
describes the configuration space registers referred to in
Description
cfg_devcsr[31:16]is status and cfg_devcsr[15:0] is device
control for the PCI Express capability structure.
cft_dev2csr[31:16] is status 2 and cfg_dev2csr[15:0] is
device control 2 for the PCI Express capability structure.
cfg_slotcsr[31:16] is the slot control and
cfg_slotcsr[15:0]is the slot status of the PCI Express
capability structure. This register is only available in root port
mode.
cfg_linkcsr[31:16] is the primary link status and
cfg_linkcsr[15:0]is the primary link control of the PCI
Express capability structure.
cfg_link2csr[31:16] is the secondary link status and
cfg_link2csr[15:0]is the secondary link control of the PCI
Express capability structure which was added for Gen2.
When tl_cfg_addr=2, tl_cfg_ctl returns the primary and
secondary link control registers, {cfg_linkcsr[15:0],
cfg_lin2csr[15:0]}, the primary link status register,
cfg_linkcsr[31:16], is available on tl_cfg_sts[46:31].
For Gen1 variants, the link bandwidth notification bit is always set
to 0. For Gen2 variants, this bit is set to 1.
Base/Primary control and status register for the PCI configuration
space.
23:16
PCI Express Base
Specification.(3’b000–3b101 correspond to 128–4096 bytes).
3’b000
15:8
cfg_busdev[12:0]
PCI Express Compiler User Guide
(Note 1)
Table 5–13
Register
Reference
Table 6–7 on
page 6–4
0x088 (Gen1)
Table 6–8 on
page 6–5
0x0A8 (Gen2)
Table 6–7 on
page 6–4
0x098 (Gen1)
Table 6–8 on
page 6–5
0x098 (Gen2)
Table 6–7 on
page 6–4
0x090 (Gen1)
Table 6–8 on
page 6–5
0x090 (Gen2)
Table 6–8 on
page 6–5
0x0B0 (Gen2,
only)
Table 6–2 on
page 6–2
0x004 (Type 0)
Table 6–3 on
page 6–3
0x004 (Type 1)
7:0
and
5–37