IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 166

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

7–6
PCI Express Compiler User Guide
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For endpoints, whenever the l2_exit, hotrst_exit, dlup_exit, or other
power-on-reset signals are asserted, srst and crst should be asserted for one or more
cycles for the soft IP implementation and for at least two clock cycles for hard IP
implementation.
Figure 7–5
Figure 7–5. Reset Signal Domains
For root ports, srst should be asserted whenever l2_exit, hotrst_exit, dlup_exit,
and power-on-reset signals are asserted. The root port crst signal should be asserted
whenever l2_exit, hotrst_exit and other power-on-reset signals are asserted. When
the perst# signal is asserted, srst and crst should be asserted for a longer period of
time to ensure that the root complex is stable and ready for link training.
Reset Signal Domains, ×8 Soft IP Implementation
The PCI Express IP core soft IP implementation (×8) has the following two reset
inputs:
npor—The npor signal is used internally for all sticky registers that may not be
reset in L2 low power mode or by the fundamental reset). npor is typically
generated by a logical OR of the power-on-reset generator and the perst signal as
specified in the PCI Express card electromechanical specification.
srst— The srst signal initiates a synchronous reset of the datapath state
machines.
crst—The crst signal initiates a synchronous reset of the nonsticky configuration
space registers.
provides a simplified view of the logic controlled by the reset signals.
npor
crst
srst
<variant>. v or .vhd
<variant> _core.v or .vhd
altpcie_hip_pipen1b.v or .vhd
Datapath State Machines of
Non-Sticky Registers
Configuration Space
Configuration Space
MegaCore Fucntion
Sticky Registers
SERDES Reset
State Machine
December 2010 Altera Corporation
Chapter 7: Reset and Clocks
Reset in Stratix V Devices