IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 324

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–18
Figure B–13. TX Transfer for A Single DWORD Write
Figure B–14. TX State Machine Is Busy with the Preceding Transaction Layer Packet Waveform
PCI Express Compiler User Guide
Descriptor
Data
Signals
Signals
Descriptor
Signals
Data
Signals
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
Figure B–13
Transaction Layer Not Ready to Accept Packet
In this example, the application transmits a 64-bit memory read transaction of six
DWORDs. Address bit 2 is set to 0. Refer to
Data transmission cannot begin if the IP core’s transaction layer state machine is still
busy transmitting the previous packet, as is the case in this example.
tx_ack
tx_req
tx_dfr
tx_ws
tx_err
tx_dv
clk
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
1
shows the IP core transmitting a memory write of one DWORD.
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
2
clk
1
3
MEMWR32
2
4
DW0
3
MEMWR64
5
Figure
4
B–14.
6
5
December 2010 Altera Corporation
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6
7
Descriptor/Data Interface
8
9
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