IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 356

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Info–4
PCI Express Compiler User Guide
February 2009
Date
Version
9.0
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Updated
Added device support for Arria II GX in both the hard and soft IP implementations. Added
preliminary support for HardCopy III and HardCopy IV E.
Added support for hard IP endpoints in the SOPC Builder design flow.
Added PCI Express reconfiguration block for dynamic reconfiguration of configuration space
registers. Updated figures to show this block.
Enhanced
RC slave module, tests for ECRC and PCI Express dynamic reconfiguration.
Changed
Improved documentation of MSI.
Added definitions of DMA read and writes status registers in
Design
Added the following signals to the hard IP implementation of root port and endpoint using
the MegaWizard Plug-In Manager design flow: tx_pipemargin, tx_pipedeemph,
tx_swing (PIPE interface), ltssm[4:0], and lane_act[3:0] (Test interface).
Added recommendation in
Avalon Configuration selects a dynamic translation table that multiple address translation
table entries be employed to avoid updating a table entry before outstanding requests
complete.
Clarified that ECC support is only available in the hard IP implementation.
Updated
Space register and all virtual channels.
Made the following corrections to description of
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The enable rate match FIFO is available for Stratix IV GX
Completion timeout is available for v2.0
MSI-X Table BAR Indicator (BIR) value can range 1:0–5:0 depending on BAR settings
Changes in
<= 4 μs, not < 4 μs; L1 acceptable latency is <= 64 μs, not < 64 μs, L1 exit latency
common clock is <= 64 μs, not < 64 μs, L1 exit latency separate clock is <= 64 μs, not <
64 μs
N_FTS controls are disabled for Stratix IV GX pending devices characterization
Example.
Table 1–8 on page 1–13
Figure 4–7 on page 4–9
Chapter 16, SOPC Builder Design Example
Chapter 15, Testbench and Design Example
“Power Management Parameters” on page
“Avalon Configuration Settings” on page 3–14
to show connections between the Type 0 Configuration
and
Changes Made
Table 1–9 on page
Chapter 3, Parameter
to demonstrate use of interrupts.
to include default instantiation of the
1–14. Removed tx_swing signal.
3–12: L0s acceptable latency is
Chapter 15, Testbench and
December 2010 Altera Corporation
Settings:
Additional Information
that when the
Revision History
SPR