IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 139

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Physical Layer Interface Signals
Table 5–32. 1-Bit Interface Signals
December 2010 Altera Corporation
tx_out[0:7]
rx_in<0:7>
pipe_mode
xphy_pll_areset
xphy_pll_locked
Note to
(1) The ×1 IP core only has lane 0. The ×4 IP core only has lanes 0–3.
Signal SOPC Builder
Table
Serial Interface Signals
5–32:
The following sections describe signals for the three possible types of physical
interfaces (1-bit, 20-bit, or PIPE). Refer to
page
of all of the PCI Express IP core variants.
Table 5–32
the Arria GX PHY, Arria II GX PHY, Stratix II GX PHY, Stratix IV GX or the
Stratix V GX PHY.
For the soft IP implementation of the ×1 IP core any channel of any transceiver block
can be assigned for the serial input and output signals. For the hard IP
implementation of the ×1 IP core the serial input and output signals must use channel
0 of the Master Transceiver Block associated with that hard IP block.
For the ×4 IP core the serial inputs (rx_in[0-3]) and serial outputs (tx_out[0-3])
must be assigned to the pins associated with the like-number channels of the
transceiver block. The signals rx_in[0]/tx_out[0] must be assigned to the pins
associated with channel 0 of the transceiver block, rx_in[1]/tx_out[1] must be
assigned to the pins associated with channel 1 of the transceiver block, and so on.
Additionally, the ×4 hard IP implementation must use the four channels of the Master
Transceiver Block associated with that hard IP block.
For the ×8 IP core the serial inputs (rx_in[0-3]) and serial outputs (tx_out[0-3])
must be assigned to the pins associated with the like-number channels of the Master
Transceiver Block. The signals rx_in[0]/tx_out[0] must be assigned to the pins
associated with channel 0 of the Master Transceiver Block, rx_in[1]/tx_out[1] must
be assigned to the pins associated with channel 1 of the Master Transceiver Block, and
so on. The serial inputs (rx_in[4-7]) and serial outputs (tx_out[4-7]) must be
5–3,
Figure 5–3 on page
I/O
describes the serial interface signals. These signals are available if you use
O
O
I
I
I
Transmit input. These signals are the serial outputs of lane 0–7.
Receive input. These signals are the serial inputs of lane 0–7.
pipe_mode selects whether the IP core uses the PIPE interface or the 1-bit
interface. Setting pipe_mode to a 1 selects the PIPE interface, setting it to 0
selects the 1-bit interface. When simulating, you can set this signal to indicate
which interface is used for the simulation. When compiling your design for an
Altera device, set this signal to 0.
Reset signal to reset the PLL associated with the PCI Express IP core.
Asserted to indicate that the IP core PLL has locked. May be used to implement an
optional reset controller to guarantee that the external PHY and PLL are stable
before bringing the PCI Express IP core out of reset. For PCI Express IP cores that
require a PLL, the following sequence of events guarantees the IP core comes out
of reset:
a. Deassert xphy_pll_areset to the PLL in the PCI Express IP core.
b. Wait for xphy_pll_locked to be asserted
c. Deassert reset signal to the PCI Express IP core
5–4, and
Figure 5–40 on page 5–47
Figure 5–1 on page
Description
5–2,
PCI Express Compiler User Guide
for pinout diagrams
Figure 5–2 on
5–55