IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 55

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Power Management
Table 3–5. Power Management Parameters (Part 2 of 2)
December 2010 Altera Corporation
Common clock
Separate clock
Electrical idle exit
(EIE) before FTS
Enable L1 ASPM
Endpoint L1
acceptable latency
L1 Exit Latency
Common clock
L1 Exit Latency
Separate clock
Parameter
Gen1: 0–255
Gen2: 0–255
Gen1: 0–255
Gen2: 0–255
3:0
On/Off
< 1 µs to > 64 µs
< 1µs to > 64 µs
< 1µs to > 64 µs
Value
L1s Active State Power Management (ASPM)
Number of fast training sequences (N_FTS)
Indicates the number of fast training sequences needed in common clock
mode. The number of fast training sequences required is transmitted to the
other end of the link during link initialization and is also used to calculate
the L0s exit latency field of the device capabilities register (0x084). If you
select the Arria GX, Arria II GX, Stratix II GX, Stratix IV GX or Stratix V GX
PHY, this parameter is disabled and set to its maximum value. If you are
using an external PHY, consult the PHY vendor's documentation to
determine the correct value for this parameter.
Indicates the number of fast training sequences needed in separate clock
mode. The number of fast training sequences required is transmitted to the
other end of the link during link initialization and is also used to calculate
the L0s exit latency field of the device capabilities register (0x084). If you
select the Arria GX, Arria II GX, Stratix II GX Stratix IV GX or Stratix V GX
PHY, this parameter is disabled and set to its maximum value. If you are
using an external PHY, consult the PHY vendor's documentation to
determine the correct value for this parameter.
Sets the number of EIE symbols sent before sending the N_FTS sequence.
Legal values are 4–8. N_FTS is disabled for Arria II GX and Stratix IV GX
devices pending device characterization.
Sets the L1 active state power management support bit in the link
capabilities register (0x08C). If you select the Arria GX, Arria II GX,
Cyclone IV GX, Stratix II GX, Stratix IV GX or Stratix V GX PHY, this option
is turned off and disabled.
This value indicates the acceptable latency that an endpoint can withstand
in the transition from the L1 to L0 state. It is an indirect measure of the
endpoint’s internal buffering. This setting is disabled for root ports. Sets the
read-only value of the endpoint L1 acceptable latency field of the device
capabilities register. It provides information to other devices which have
turned On the Enable L1 ASPM option. If you select the Arria GX,
Arria II GX, Cyclone IV GX, Stratix II GX, Stratix IV GX or Stratix V GX
PHY, this option is turned off and disabled.
Indicates the L1 exit latency for the separate clock. Used to calculate the
value of the L1 exit latency field of the device capabilities register (0x084). If
you select the Arria GX, Arria II GX, Cyclone IV GX, Stratix II GX,
Stratix IV GX or Stratix V GX PHY this parameter is disabled and set to its
maximum value. If you are using an external PHY, consult the PHY vendor's
documentation to determine the correct value for this parameter.
Indicates the L1 exit latency for the common clock. Used to calculate the
value of the L1 exit latency field of the device capabilities register (0x084). If
you select the Arria GX, Arria II GX, Cyclone IV GX, Stratix II GX,
Stratix IV GX or Stratix V GX PHY, this parameter is disabled and set to its
maximum value. If you are using an external PHY, consult the PHY vendor's
documentation to determine the correct value for this parameter.
Description
PCI Express Compiler User Guide
3–13