IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 185

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 9: Optional Features
Active State Power Management (ASPM)
Active State Power Management (ASPM)
December 2010 Altera Corporation
Exit Latency
1
The PCI Express protocol mandates link power conservation, even if a device has not
been placed in a low power state by software. ASPM is initiated by software but is
subsequently handled by hardware. The IP core automatically shifts to one of two low
power states to conserve power:
■
■
In the L2 state, only auxiliary power is available; main power is off. Because the
auxiliary power supply is insufficient to run an FPGA, Altera FPGAs provide
pseudo-support for this state. The pm_auxpwr signal, which indicates that auxiliary
power has been detected, can be hard-wired high.
An endpoint can exit the L0s or L1 state by asserting the pm_pme signal. Doing so,
initiates a power_management_event message which is sent to the root complex. If the
IP core is in theL0s or L1 state, the link exits the low-power state to send this message.
The pm_pme signal is edge-senstive. If the link is in the L2 state, a Beacon (or Wake#) is
generated to reinitialize the link before the core can generate the
power_management_event message. Wake# is hardwired to 0 for root ports.
How quickly a component powers up from a low-power state, and even whether a
component has the right to transition to a low power state in the first place, depends
on
acceptable
A component’s exit latency is defined as the time it takes for the component to awake
from a low-power state to L0, and depends on the SERDES PLL synchronization time
and the common clock configuration programmed by software. A SERDES generally
has one transmit PLL for all lanes and one receive PLL per lane.
■
L1 Exit
L0s ASPM—The PCI Express protocol specifies the automatic transition to L0s. In
this state, the IP core transmits electrical idle but can maintain an active reception
interface because only one component across a link moves to a lower power state.
Main power and reference clocks are maintained.
1
L1 ASPM—Transition to L1 is optional and conserves even more power than L0s.
In this state, both sides of a link power down together, so that neither side can
send or receive without first transitioning back to L0.
1
Transmit PLL—When transmitting, the transmit PLL must be locked.
L0s ASPM can be optionally enabled when using the Arria GX,
Cyclone IV GX, HardCopy IV GX, Stratix II GX, Stratix IV GX, or
Stratix V GX internal PHY. It is supported for other device families to the
extent allowed by the attached external PHY device.
L1 ASPM is not supported when using the Arria GX, Cyclone IV GX,
HardCopy IV GX, Stratix II GX, Stratix IV GX, or Stratix V GX internal
PHY. It is supported for other device families to the extent allowed by the
attached external PHY device.
Latency, recorded in the
latency, recorded in the
Device Capabilities
Link Capabilities
register, and
register.
PCI Express Compiler User Guide
Endpoint L0s
9–3