IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 110

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–26
Table 5–7. Reset and Link Training Signals (Part 3 of 3)
PCI Express Compiler User Guide
dlup_exit
rc_pll_locked
Signal
Reset Details
The following description applies to all devices except Stratix V. Refer to
Details for Stratix V Devices” on page 5–27
The hard IP implementation (×1, ×4, and ×8) or the soft IP implementation (×1 and
×4) have three reset inputs: npor, srst, and crst. npor is used internally for all sticky
registers that may not be reset in L2 low power mode or by the fundamental reset).
npor is typically generated by a logical OR of the power-on-reset generator and the
perst signal as specified in the PCI Express card electromechanical specification. The
srst signal is a synchronous reset of the datapath state machines. The crst signal is a
synchronous reset of the nonsticky configuration space registers. For endpoints,
whenever the l2_exit, hotrst_exit, dlup_exit, or other power-on-reset signals are
asserted, srst and crst should be asserted for one or more cycles for the soft IP
implementation and for at least 2 clock cycles for hard IP implementation.
Figure 5–26
Figure 5–26. Reset Signal Domains
I/O
O
O
This signal is active for one pld_clk cycle when the IP core exits the DLCSM DLUP state. In
endpoints, this signal should cause the application to assert a global reset (crst and srst in
the hard IP implementation and ×1 and ×4 soft IP implementation, or rstn in ×8 the soft IP
implementation). In root ports, this signal should cause the application to assert srst, but not
crst. This signal is active low and otherwise remains high.
Indicates that the SERDES receiver PLL is in locked mode with the reference clock. In pipe
simulation mode this signal is always asserted.
provides a simplified view of the logic controlled by the reset signals.
npor
crst
srst
<variant>. v or .vhd
<variant> _core.v or .vhd
altpcie_hip_pipen1b.v or .vhd
Description
Datapath State Machines of
Non-Sticky Registers
Configuration Space
Configuration Space
MegaCore Fucntion
for Stratix V devices.
Sticky Registers
SERDES Reset
State Machine
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Avalon-ST Interface
“Reset