IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 215

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 13: Reconfiguration and Offset Cancellation
Transceiver Offset Cancellation
Transceiver Offset Cancellation
December 2010 Altera Corporation
f
1
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature (PVT). These process
variations result in analog voltages that can be offset from required ranges. When you
implement the PCI Express IP core in a Arria II GX, HardCopy IV GX, Cyclone IV GX,
Stratix IV GX, device using the internal PHY, you must compensate for this variation
by including the ALTGX_RECONFIG megafunction in your design. When you
generate your ALTGX_RECONFIG module the Offset cancellation for receiver
channels option is On by default. This feature is all that is required to ensure that the
transceivers operate within the required ranges, but you can choose to enable other
features such as the Analog controls option if your system requires this. You must
connect, the reconfig_fromgxb and reconfig_togxb busses and the necessary clocks
between the ALTGX instance and the ALTGX_RECONFIG instance, as
illustrates.
The offset cancellation circuitry requires the following two clocks.
■
■
Refer to the appropriate device handbook to determine the frequency range for your
device as follows:
Transceivers
Volume 2 of the Stratix IV Device Handbook, or
devices.
The <variant>_plus hard IP PCI Express endpoint automatically includes the circuitry
for offset cancellation, you do not have to add this circuitry manually.
fixedclk —This is a free running clock whose frequency must be 125 MHz. It
cannot be generated from refclk.
reconfig_clk— The correct frequency for this clock is device dependent
in Volume 2 of the Cyclone IV Device Handbook,
Transceiver Architecture
in Volume II of the Arria II Device Handbook,
Altera PHY IP User Guide
Transceiver Architecture
PCI Express Compiler User Guide
Figure 13–1
for Stratix V
in
13–9