IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 120

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–36
Figure 5–34. tl_cfg_ctl Timing for Stratix V Devices
Figure 5–35. tl_cfg_ctl Timing for Stratix V Devices
Table 5–15. Multiplexed Configuration Register Information Available on tl_cfg_ctl (Part 1 of 2)
PCI Express Compiler User Guide
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
Address
Max Read Req Size
cfg_devcsr[14:12]=
tl_cfg_sts[53:0]
8’h00
8h’00
8’h00
31:24
Configuration Space Register Access Timing - Stratix V
Figure 5–34
Figure 5–35
Configuration Space Register Access
The tl_cfg_ctl signal is a multiplexed bus that contains the contents of configuration
space registers as shown in
is accessed in round robin order where tl_cfg_add indicates which register is being
accessed.
multiplexed on tl_cfg_ctl.
tl_cfg_add[3:0]
pld_clk
tl_cfg_ctl[31:0]
cfg_slotcsr[31:16]
12’h000
12’h000
cfg_linkscr[15:0]
cfg_msixcsr[15:0]
cfg_seccsr[15:0]
core_clk
cfg_devcsr[15:0]
Table 5–15
(2)
shows the timing for updates to the tl_cfg_ctlbus in Stratix V devices.
shows the timing for updates to the tl_cfg_sts bus in Stratix V devices.
20’h00000
20’h00000
data0
cfg_devcsr[7:5]=
Max Payload
shows the layout of configuration information that is
data0
addr0
cfg_np_bas[11:0]
23:16
data1
Table
data1
addr1
cfg_prmcsr[15:0]
cfg_pr_bas[31:0]
cfg_pr_lim[31:0]
cfg_pmcsr[31:0]
data2
(2)
5–13. Information stored in the configuration space
data2
addr2
data3
cfg_secbus[7:0]
cfg_tcvcmap[23:0]
addr3
data3
data4
cfg_io_bas[19:0]
cfg_io_lim[19:0]
15:8
data4
addr4
cfg_link2csr[15:0]
data5
cfg_dev2csr[15:0]
cfg_slotcsr[15:0]
cfg_msicsr[15:0]
data5
addr5
cfg_pr_bas[43:32]
cfg_pr_lim[43:32]
cfg_np_lim[11:0]
December 2010 Altera Corporation
data6
cfg_rootcsr[7:0]
cfg_subbus[7:0]
Chapter 5: IP Core Interfaces
data6
addr6
(Note 1)
Avalon-ST Interface
7:0