IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 248

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

15–20
Table 15–14. Write Descriptor 0
Table 15–15. Write Descriptor 1
Table 15–16. Write Descriptor 2
Table 15–17. DMA Control Register Setup for DMA Write
PCI Express Compiler User Guide
DW2
DW3
Data
Buffer 0
DW0
DW1
DW2
DW3
Data
Buffer 1
DW0
DW1
DW2
DW3
Data
Buffer 2
DW0
DW1
DW2
DW3
0x0
0x4
0x8
0xc
0x830
0x834
0x838
0x83c
0x057A0
0x820
0x824
0x828
0x82c
0x02800
0x818
0x81c
0x1800
Control Register
Offset in DMA
Shared Memory
Shared Memory
Offset in BFM
Offset in BFM
(BAR2)
2. Sets up the chaining DMA descriptor header and starts the transfer data from the
endpoint memory to the BFM shared memory. The transfer calls the procedure
dma_set_header which writes four dwords, DW0:DW3
DMA write register module.
After writing the last dword, DW3, of the descriptor header, the DMA write starts
the three subsequent data transfers.
3
0
0x800
2
1,024
0
0
0x2800
Increment by 1 from
0x2525_0001
644
0
0
0x057A0
Increment by 1 from
0x3535_0001
0
0x1800
Increment by 1 from
0x1515_0001
Value
Value
Value
Number of descriptors and control bits as described in
page 15–14
BFM shared memory descriptor table upper address value
BFM shared memory descriptor table lower address value
Last valid descriptor
Transfer length in DWORDS and control bits as described in
page 15–18
Endpoint address
BFM shared memory data buffer 1 upper address value
BFM shared memory data buffer 1 lower address value
Data content in the BFM shared memory from address: 0x02800
Endpoint address
BFM shared memory data buffer 2 upper address value
BFM shared memory data buffer 2 lower address value
Transfer length in DWORDS and control bits as described in
Table 15–6 on page 15–14
Data content in the BFM shared memory from address: 0x057A0
BFM shared memory data buffer 0 upper address value
BFM shared memory data buffer 1 lower address value
Data content in the BFM shared memory from address:
0x01800–0x1840
Description
Description
Description
Chapter 15: Testbench and Design Example
(Table
December 2010 Altera Corporation
Table 15–5 on
15–17), into the
Test Driver Module
on