IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 79

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
PCI Express Avalon-MM Bridge
Figure 4–11. PCI Express Avalon-MM Bridge Address Translation
Note to
(1) N is the number of pass-through bits (BAR specific). M is the number of Avalon-MM address bits. P is the number of PCI Express address bits
December 2010 Altera Corporation
(64/32)
Figure
4–11:
f
Inside PCI Express MegaCore Function
BAR0 (or 0:1)
BAR1
BAR2
BAR3
BAR4
BAR5
translation entries in the address translation table are configurable by the user or by
SOPC Builder. Each entry corresponds to a PCI Express BAR. The BAR hit
information from the request header determines the entry that is used for address
translation.
translation process.
The Avalon-MM RX master module port has an 8-byte datapath. This 8-byte wide
datapath means that native address alignment Avalon-MM slaves that are connected
to the RX master module port will have their internal registers at 8-byte intervals in
the PCI Express address space. When reading or writing a native address alignment
Avalon-MM Slave (such as the SOPC Builder DMA controller core) the PCI Express
address should increment by eight bytes to access each successive register in the
native address slave.
For more information, refer to the “Native Address Alignment and Dynamic Bus
Sizing” section in the
in volume 4 of the Quartus II Handbook.
Avalon-MM-to-PCI Express Address Translation
The Avalon-MM address of a received request on the TX Slave Module port is
translated to the PCI Express address before the request packet is sent to the
transaction layer. This address translation process proceeds by replacing the MSB bits
of the Avalon-MM address with the value from a specific translation table entry; the
LSB bits remain unchanged. The number of MSB bits to be replaced is calculated
based on the total address space of the upstream PCI Express devices that the PCI
Express IP core can access.
P-1
PCI Express Address
High
Figure 4–11
N N-1
Low
System Interconnect Fabric for Memory-Mapped Interfaces
depicts the PCI Express Avalon-MM bridge address
0
selects Avalon-MM
Matched BAR
address
Low address bits unchanged
(BAR-specific number of bits)
(Note 1)
Hard-coded BAR-specific
Avalon-MM Addresses
Avalon Address B0
Avalon Address B1
Avalon Address B2
Avalon Address B3
Avalon Address B4
Avalon Address B5
Avalon-MM Address
BAR-specific Number of
M-1
High Avalon-MM Bits
High
PCI Express Compiler User Guide
N N-1
Low
0
chapter
4–21