IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 60

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–2
Figure 4–1. IP core PCI Express Layers
Application Interfaces
PCI Express Compiler User Guide
Avalon-ST Application Interface
Tx Port
Rx Port
f
To Application Layer
PCI Express IP Core
Application Interfaces
Avalon-MM Interface
Figure 4–1
Avalon-ST Interface
This chapter provides an overview of the architecture of the Altera PCI Express IP
core. It includes the following sections:
■
■
■
■
■
■
You can generate the PCI Express IP core with the following application interfaces:
■
■
The
You can create a PCI Express root port or endpoint using the MegaWizard Plug-In
Manager to specify the Avalon-ST interface. It includes a PCI Express Avalon-ST
adapter module in addition to the three PCI Express layers.
Data/Descriptor
Interface
Application Interfaces
Transaction Layer
Data Link Layer
Physical Layer
PCI Express Avalon-MM Bridge
Completer Only PCI Express Endpoint Single DWord
Avalon-ST Application Interface
Avalon-MM Interface
Appendix B
or
or
broadly describes the roles of each layer of the PCI Express IP core.
describes the Descriptor/Data interface
With information sent
by the application
layer, the transaction
layer generates a TLP,
which includes a
header and, optionally,
a data payload.
The transaction layer
disassembles the
transaction and
transfers data to the
application layer in a
form that it recognizes.
Transaction Layer
The data link layer
ensures packet
integrity, and adds a
sequence number and
link cyclic redundancy
code (LCRC) check to
the packet.
The data link layer
verifies the packet's
sequence number and
checks for errors.
Data Link Layer
The physical layer
encodes the packet
and transmits it to the
receiving device on the
other side of the link.
The physical layer
decodes the packet
and transfers it to the
data link layer.
Physical Layer
December 2010 Altera Corporation
Chapter 4: IP Core Architecture
To Link
Application Interfaces
Tx
Rx