IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 35

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Simulate the Design
Simulate the Design
Example 2–1. Excerpts from Transcript of Successful Simulation Run
altpll_component.pll0
# INFO:
# INFO: Core Clk Frequency: 251.00 Mhz
# INFO: 3608 ns
# INFO: 3644 ns EP LTSSM State: POLLING.ACTIVE
# INFO: 3660 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 3692 ns
# INFO: 6012 ns
# INFO: 6108 ns
# INFO: 7388 ns
# INFO: 7420 ns
# INFO: 7900 ns
# INFO: 8316 ns
# INFO: 8508 ns
# INFO: 9004 ns
# INFO: 9196 ns
# INFO: 9356 ns
# INFO: 9548 ns
# INFO: 9964 ns
# INFO: 11052 ns
# INFO: 11276 ns
# INFO: 11356 ns
# INFO: 11580 ns
December 2010 Altera Corporation
Time: 56000
Instance: top_chaining_testbench.ep.epmap.pll_250mhz_to_500mhz.
As
<working_dir>\top_examples\chaining_dma\testbench directory. Follow these
steps to run the chaining DMA testbench.
1. Start your simulation tool. This example uses the ModelSim
2. In the testbench directory,
Example 2–1
transcript illustrates, the simulation includes the following stages:
■
■
■
■
EP LTSSM State: DETECT.ACTIVE
RP LTSSM State: POLLING.ACTIVE
RP LTSSM State: POLLING.CONFIG
EP LTSSM State: POLLING.CONFIG
EP LTSSM State: CONFIG.LINKWIDTH.START
RP LTSSM State: CONFIG.LINKWIDTH.START
EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
RP LTSSM State: CONFIG.LANENUM.WAIT
EP LTSSM State: CONFIG.LANENUM.WAIT
EP LTSSM State: CONFIG.LANENUM.ACCEPT
RP LTSSM State: CONFIG.LANENUM.ACCEPT
RP LTSSM State: CONFIG.COMPLETE
EP LTSSM State: CONFIG.COMPLETE
EP LTSSM State: CONFIG.IDLE
RP LTSSM State: CONFIG.IDLE
RP LTSSM State: L0
EP LTSSM State: L0
Figure 2–4
1
<working_dir>\top_examples\chaining_dma\testbench, type the following
command:
do runtb.do r
Link training
Configuration
DMA reads and writes
Root port to endpoint memory reads and writes
This script compiles the testbench for simulation and runs the chaining DMA
tests.
464 ns Completed initial configuration of Root Port.
The endpoint chaining DMA design example DMA controller requires the
use of BAR2 or BAR3.
shows the a partial transcript from a successful simulation. As this
illustrates, the scripts to run the simulation files are located in the
PCI Express Compiler User Guide
®
software.
2–9