IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 59

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
1
This chapter describes the architecture of the PCI Express Compiler. For the hard IP
implementation, you can design an endpoint using the Avalon-ST interface or
Avalon-MM interface, or a root port using the Avalon-ST interface. For the soft IP
implementation, you can design an endpoint using the Avalon-ST, Avalon-MM or
Descriptor/Data interface. All configurations contain a transaction layer, a data link
layer, and a PHY layer with the following functions:
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PCI Express soft IP endpoints comply with the
1.1. The PCI Express hard IP endpoint and root port comply with the
Specification 1.1. 2.0, or
Transaction Layer—The transaction layer contains the configuration space, which
manages communication with the application layer: the receive and transmit
channels, the receive buffer, and flow control credits. You can choose one of the
following two options for the application layer interface from the MegaWizard
Plug-In Manager design flow:
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■
You can choose the Avalon-MM interface from the SOPC Builder flow.
Data Link Layer—The data link layer, located between the physical layer and the
transaction layer, manages packet transmission and maintains data integrity at the
link level. Specifically, the data link layer performs the following tasks:
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■
■
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Physical Layer—The physical layer initializes the speed, lane numbering, and lane
width of the PCI Express link according to packets received from the link and
directives received from higher layers.
Avalon-ST Interface
Descriptor/Data Interface (not recommended for new designs)
Manages transmission and reception of data link layer packets
Generates all transmission cyclical redundancy code (CRC) values and checks
all CRCs during reception
Manages the retry buffer and retry mechanism according to received
ACK/NAK data link layer packets
Initializes the flow control mechanism for data link layer packets and routes
flow control credits to and from the transaction layer
2.1.
PCI Express Base Specification 1.0a, or
4. IP Core Architecture
PCI Express Compiler User Guide
PCI Express Base