IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 27

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Parameterize the PCI Express
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
This section provides step-by-step instructions to help you quickly set up and
simulate the PCI Express IP core testbench. The PCI Express IP core provides
numerous configuration options. The parameters chosen in this chapter are the same
as those chosen in the
the Altera website. If you choose the parameters specified in this chapter, you can run
all of the tests included in the
following sections show you how to instantiate the PCI Express IP core by completing
the following steps:
1.
2.
3.
4.
5.
This section guides you through the process of parameterizing the PCI Express IP core
as an endpoint, using the same options that are chosen in
Design
1. On the Tools menu, click MegaWizard Plug-In Manager. The MegaWizard
2. Select Create a new custom megafunction variation and click Next.
3. In Which device family will you be using? Select the Stratix IV device family.
4. Expand the Interfaces directory under Installed Plug-Ins by clicking the + icon
5. Select the output file type for your design. This IP core supports VHDL and
6. Specify a variation name for output files <working_dir>\<variation name>. For this
7. Click Next to display the Parameter Settings page for the PCI Express IP core.
Parameterize the PCI Express
View Generated Files
Simulate the Design
Constrain the Design
Compile for the Design
Plug-In Manager appears.
left of the directory name, expand PCI Express, then click PCI Express
Compiler<version_number>
Verilog HDL. For this example, choose Verilog HDL.
walkthrough, specify top.v for the name of the IP core files: <working_dir>\top.v.
1
f
Example. Complete the following steps to specify the parameters:
You can change the page that the MegaWizard Plug-In Manager displays by
clicking Next or Back at the bottom of the dialog box. You can move
directly to a named page by clicking the Parameter Settings, EDA, or
Summary tab.
For further details about the parameters settings, refer to
Parameter
Settings.
PCI Express High-Performance Reference Design
Chapter 15, Testbench and Design
2. Getting Started
Chapter 15, Testbench and
PCI Express Compiler User Guide
Example. The
Chapter 3,
available on