IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 107

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–5. Clock Signals Hard IP Implementation
Table 5–6. Clock Signals Soft IP Implementation
December 2010 Altera Corporation
refclk
pld_clk
core_clk_out
p_clk
clk250_out
clk500_out
Note to
(1) These clock signals are illustrated by
refclk
clk125_in
clk125_out
clk250_in
clk250_out
Note to
(1) Refer to
Signal
Table
Table
Signal
Clock Signals—Hard IP Implementation
Clock Signals—Soft IP Implementation
Figure 7–9 on page 7–12
5–5:
5–6:
Table 5–5
IP implementation.
Refer to
for each PCI Express IP core.
I/O
I/O
O
O
O
I
I
I
O
O
I
I
I
Reference clock for the IP core. It must be the frequency specified on the System Settings
page accessible from the Parameter Settings tab using the parameter editor.
Clocks the application layer and part of the adapter. You must drive this clock from
core_clk_out.
This is a fixed frequency clock used by the data link and transaction layers. To meet PCI
Express link bandwidth constraints, it has minimum frequency requirements which are
outlined in
This is used for simulation only, and is derived from the refclk. It is the PIPE interface clock
used for PIPE mode simulation.
This is used for simulation only. The testbench uses this to generate p_clk.
This is used for simulation only. The testbench uses this to generate p_clk.
Reference clock for the IP core. It must be the frequency specified on the System Settings
page accessible from the Parameter Settings tab using the parameter editor.
Input clock for the ×1 and ×4 IP core. All of the IP core I/O signals (except refclk,
clk125_out, and npor) are synchronous to this clock signal. This signal must be connected
to the clk125_out signal.
Output clock for the ×1 and ×4 IP core. 125-MHz clock output derived from the refclk input.
This signal is not on the ×8 IP core.
Input clock for the ×8 IP core. All of the IP core I/O signals (except refclk, clk250_out, and
npor) are synchronous to this clock signal. This signal must be connected to the clk250_out
signal.
Output from the ×8 IP core. 250 MHz clock output derived from the refclk input. This signal
is only on the ×8 IP core.
Chapter 7, Reset and Clocks
describes the clock signals that comprise the clock interface used in the hard
Figure 7–7 on page
Table
12–4.
(Note 1)
(Note 1)
7–9.
for a complete description of the clock interface
Description
Description
PCI Express Compiler User Guide
5–23