IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 195

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Throughput of Posted Writes
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
Throughput analysis requires that you understand the Flow Control Loop, shown in
“Flow Control Update Loop” on page
Loop and strategies to improve throughput. It covers the following topics:
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The throughput of posted writes is limited primarily by the Flow Control Update loop
shown in
possible, and the completer of the writes consumes the data as quickly as possible,
then the Flow Control Update loop may be the biggest determining factor in write
throughput, after the actual bandwidth of the link.
Figure 11–1
communicating PCI Express ports:
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As the PCI Express specification describes, each transmitter, the write requester in this
case, maintains a credit limit register and a credits consumed register. The credit
limit register is the sum of all credits issued by the receiver, the write completer in
this case. The credit limit register is initialized during the flow control initialization
phase of link initialization and then updated during operation by Flow Control (FC)
Update DLLPs. The credits consumed register is the sum of all credits consumed by
packets transmitted. Separate credit limit and credits consumed registers exist for
each of the six types of Flow Control:
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Throughput of Posted Writes
Throughput of Non-Posted Reads
Write Requester
Write Completer
Posted Headers
Posted Data
Non-Posted Headers
Non-Posted Data
Completion Headers
Completion Data
Figure
shows the main components of the Flow Control Update loop with two
11–1. If the requester of the writes sources the data as quickly as
11–2. This section discusses the Flow Control
11. Flow Control
PCI Express Compiler User Guide