IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 221

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 14: External PHYs
External PHY Support
Figure 14–4. 8-bit DDR Mode with a Source Synchronous Transmit Clock
December 2010 Altera Corporation
8-bit SDR Mode
External connection
in user logic
clk125_out
clk125_in
refclk (pclk)
txclk
txdata
An edge detect circuit detects the relationships between the 125 MHz clock and the
250 MHz rising edge to properly sequence the 16-bit data into the 8-bit output
register.
Figure 14–5
included in the file <variation name>.v or <variation name>.vhd and includes a PLL.
refclk (pclk from the external PHY) drives the PLL inclock. The PLL has the
following outputs:
■
■
rxdata
A 125 MHz output derived from the 250 MHz refclk used as the clk125_in for
the core and also to transition the incoming 8-bit data into a 16-bit register for the
rest of the logic.
A 250 MHz early output that is skewed early in relation to the refclk that is used to
clock an 8-bit SDR transmit data output register. The early clock PLL output clocks
the transmit data output register. The early clock is required to meet the specified
clock-to-out times for the common clock. You may need to adjust the phase shift
for your specific PHY and board delays. To alter the phase shift, copy the PLL
source file referenced in your variation file from the <path>/ip/PCI Express
Compiler/lib directory, where <path> is the directory in which you installed the
PCI Express Compiler, to your project directory. Then use the MegaWizard Plug-In
Manager in the Quartus II software to edit the PLL source file to set the required
phase shift. Then add the modified PLL source file to your Quartus II project.
illustrates the implementation of the 8-bit SDR mode. This mode is
A
D
Q
Q
Mode 3
Q
Q
& Sync
Detect
DDIO
Edge
ENB
1
4
ENB
1
PLL
4
ENB
Q
Q
A
D
A
D
1
4
Q
Q
1
4
ENB
clk250_early
A
D
tlp_clk
txdata_h
txdata_l
clk125_in
tlp_clk
refclk
MegaCore Function
PCI Express
PCI Express Compiler User Guide
clk125_out
14–5