IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 267

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
BFM Procedures and Functions
Table 15–30. ebfm_cfgrd_nowt Procedure
Table 15–31. ebfm_cfg_rp_ep Procedure (Part 1 of 2)
December 2010 Altera Corporation
Location
Syntax
Arguments bus_num
Location
Syntax
Arguments
BFM Configuration Procedures
ebfm_cfgrd_nowt(bus_num, dev_num, fnc_num, regb_ad, regb_ln, lcladdr)
dev_num
fnc_num
regb_ad
regb_ln
lcladdr
altpcietb_bfm_configure.v or altpcietb_bfm_configure.vhd
ebfm_cfg_rp_ep(bar_table, ep_bus_num, ep_dev_num, rp_max_rd_req_size,
display_ep_config, addr_map_4GB_limit)
bar_table
altpcietb_bfm_rdwr.v or altpcietb_bfm_rdwr.vhd
ebfm_cfgrd_nowt Procedure
The ebfm_cfgrd_nowt procedure reads up to four bytes of data from the specified
configuration register and stores the data in the BFM shared memory. This procedure
returns as soon as the VC interface module has accepted the transaction, allowing
other reads to be issued in the interim. Use this procedure only when successful
completion status is expected and a subsequent read or write with a wait can be used
to guarantee the completion of this operation.
The following procedures are available in altpcietb_bfm_configure. These
procedures support configuration of the root port and endpoint configuration space
registers.
All VHDL arguments are subtype natural and are input-only unless specified
otherwise. All Verilog HDL arguments are type integer and are input-only unless
specified otherwise.
ebfm_cfg_rp_ep Procedure
The ebfm_cfg_rp_ep procedure configures the root port and endpoint configuration
space registers for operation. Refer to
this procedure.
PCI Express bus number of the target device.
PCI Express device number of the target device.
Function number in the target device to be accessed.
Byte-specific address of the register to be written.
Length, in bytes, of the data written. Maximum length is four bytes. The regb_ln and
regb_ad arguments cannot cross a DWORD boundary.
BFM shared memory address where the read data should be placed.
Address of the endpoint bar_table structure in BFM shared memory. This
routine populates the bar_table structure. The bar_table structure stores
the size of each BAR and the address values assigned to each BAR. The address
of the bar_table structure is passed to all subsequent read and write
procedure calls that access an offset from a particular BAR.
Table 15–31
for a description the arguments for
PCI Express Compiler User Guide
15–39