IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 295

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 16: SOPC Builder Design Example
Simulate the SOPC Builder System
Example 16–1. Transcript from Simulation of Requester/Completer PCI Express Hard IP Implementation
# INFO: 464 ns Completed initial configuration of Root Port.
# INFO: 3641 ns EP LTSSM State: DETECT.ACTIVE
# INFO: 3657 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 3689 ns EP LTSSM State: POLLING.ACTIVE
# INFO: 6905 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 9033 ns RP LTSSM State: POLLING.CONFIG
# INFO: 9353 ns EP LTSSM State: POLLING.CONFIG
# INFO: 10441 ns EP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 10633 ns RP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 11273 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 11801 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 12121 ns RP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 12745 ns EP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 12937 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 13081 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 13401 ns RP LTSSM State: CONFIG.COMPLETE
# INFO: 13849 ns EP LTSSM State: CONFIG.COMPLETE
# INFO: 14937 ns EP LTSSM State: CONFIG.IDLE
# INFO: 15129 ns RP LTSSM State: CONFIG.IDLE
# INFO: 15209 ns RP LTSSM State: L0
# INFO: 15465 ns
# INFO: 21880 ns EP PCI Express Link Status Register (1041):
# INFO: 21880 ns
# INFO: 21880 ns
# INFO: 22769 ns RP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 23177 ns EP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 23705 ns EP LTSSM State: RECOVERY.RCVRCFG
# INFO: 23873 ns RP LTSSM State: RECOVERY.RCVRCFG
# INFO: 25025 ns RP LTSSM State: RECOVERY.IDLE
# INFO: 25305 ns EP LTSSM State: RECOVERY.IDLE
# INFO: 25385 ns EP LTSSM State: L0
# INFO: 25537 ns RP LTSSM State: L0
# INFO: 26384 ns
# INFO: 27224 ns EP PCI Express Link Control Register (0040):
# INFO: 27224 ns
# INFO: 28256 ns EP PCI Express Capabilities Register (0001):
# INFO: 28256 ns
# INFO: 28256 ns
# INFO: 28256 ns EP PCI Express Link Capabilities Register (0103F441):
# INFO: 28256 ns
# INFO: 28256 ns
# INFO: 28256 ns
# INFO: 28256 ns
# INFO: 33008 ns BAR1:0 4 KBytes 00000001 00000000 Prefetchable
# INFO: 33008 ns BAR2
# INFO: 34104 ns Completed configuration of Endpoint BARs.
# INFO: 35064 ns Starting Target Write/Read Test.
# INFO: 35064 ns
# INFO: 35064 ns Length = 004096, Start Offset = 000000
# INFO: 47272 ns
# INFO: 47272 ns Starting DMA Read/Write Test.
# INFO: 47272 ns
# INFO: 47272 ns Length = 004096, Start Offset = 000000
# INFO: 55761 ns Interrupt Monitor: Interrupt INTA Asserted
# INFO: 55761 ns Clear Interrupt INTA
# INFO: 56737 ns Interrupt Monitor: Interrupt INTA Deasserted
# INFO: 66149 ns MSI recieved!
#INFO: 66149 ns
December 2010 Altera Corporation
Target Write and Read compared okay!
Example 16–1
Target BAR = 0
Setup BAR = 2
EP LTSSM State: L0
Negotiated Link Width: x4
DMA Read and Write compared okay!
Supported Link Speed: 2.5GT/s
Slot Clock Config: System Reference Clock Used
Capability Version: 1
Maximum Link Width: x4
Common Clock Config: System Reference Clock Used
Current Link Speed: 2.5GT/s
32 KBytes
L1 Entry: Not Supported
L0s Entry: Supported
provides a partial transcript from a successful simulation.
Port Type: Native Endpoint
00200000 Non-Prefetchable
PCI Express Compiler User Guide
16–11