IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 61

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
Application Interfaces
Figure 4–2. IP core with PCI Express Avalon-ST Interface Adapter
Note to
(1) Stratix V devices do not require the adapter module.
December 2010 Altera Corporation
Figure
Avalon-ST
Avalon-ST
Tx Port
4–2:
Rx Port
The PCI Express Avalon-ST adapter maps PCI Express transaction layer packets
(TLPs) to the user application RX and TX busses.
Figure 4–3
Express IP core. In both cases the adapter maps the user application Avalon-ST
interface to PCI Express TLPs. The hard IP and soft IP implementations differ in the
following respects:
■
To Application Layer
The hard IP implementation includes dedicated clock domain crossing logic
between the PHYMAC and data link layers. In the soft IP implementation you can
specify one or two clock domains for the IP core.
PCI Express IP Core
Avalon-ST
Adapter
Note (1)
and
With information sent
by the application
layer, the transaction
layer generates a TLP,
which includes a
header and, optionally,
a data payload.
The transaction layer
disassembles the
transaction and
transfers data to the
application layer in a
form that it recognizes.
Figure 4–4
Transaction Layer
illustrate the hard and soft IP implementations of the PCI
The data link layer
ensures packet
integrity, and adds a
sequence number and
link cyclic redundancy
code (LCRC) check to
the packet.
The data link layer
verifies the packet's
sequence number and
checks for errors.
Data Link Layer
Figure 4–2
The physical layer
encodes the packet
and transmits it to the
receiving device on the
other side of the link.
The physical layer
decodes the packet
and transfers it to the
data link layer.
Physical Layer
illustrates this interface.
PCI Express Compiler User Guide
To Link
Rx
Tx
4–3