IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 141

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Physical Layer Interface Signals
Table 5–33. PIPE Interface Signals (Part 1 of 2)
December 2010 Altera Corporation
txdata<n>_ext[15:0]
txdatak<n>_ext[1:0]
txdetectrx<n>_ext
txelecidle<n>_ext
txcompl<n>_ext
rxpolarity<n>_ext
powerdown<n>_ext[1:0]
tx_pipemargin
tx_pipedeemph
rxdata<n>_ext[15:0]
rxdatak<n>_ext[1:0]
rxvalid<n>_ext
Signal SOPC Builder
(1)
(1) (2)
(1)
(1)
(1)
for simulation of the PIPE interface for variations using an internal transceiver. In
Table
table. Refer to
PIPE interface signalling for use with specific external PHYs. The modifications
include DDR signalling and source synchronous clocking in the TX direction.
(1) (2)
(1) (2)
(1)
(1)
5–33, signals that include lane number 0 also exist for lanes 1-7, as marked in the
Chapter 14, External PHYs
I/O
O
O
O
O
O
O
O
O
O
I
I
I
Transmit data <n> (2 symbols on lane <n>). This bus transmits data on
lane <n>. The first transmitted symbol is txdata_ext[7:0] and the
second transmitted symbol is txdata0_ext[15:8]. For the 8-bit PIPE
mode only txdata<n>_ext[7:0] is available.
Transmit data control <n> (2 symbols on lane <n>). This signal serves
as the control bit for txdata<n>_ext; txdatak<n>_ext[0] for the
first transmitted symbol and txdatak<n>_ext[1] for the second
(8B10B encoding). For 8-bit PIPE mode only the single bit signal
txdatak<n>_ext is available.
Transmit detect receive <n>. This signal tells the PHY layer to start a
receive detection operation or to begin loopback.
Transmit electrical idle <n>. This signal forces the transmit output to
electrical idle.
Transmit compliance <n>. This signal forces the running disparity to
negative in compliance mode (negative COM character).
Receive polarity <n>. This signal instructs the PHY layer to do a polarity
inversion on the 8B10B receiver decoding block.
Power down <n>. This signal requests the PHY to change its power state
to the specified state (P0, P0s, P1, or P2).
Transmit V
value for this signal based on the value from the Link Control 2 Register.
Available for simulation only.
Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it
selects the transmitter de-emphasis:
■
■
The PCI Express IP core hard IP sets the value for this signal based on
the indication received from the other end of the link during the Training
Sequences (TS). You do not need to change this value.
Receive data <n> (2 symbols on lane <n>). This bus receives data on
lane <n>. The first received symbol is rxdata<n>_ext[7:0] and the
second is rxdata<n>_ext[15:8]. For the 8 Bit PIPE mode only
rxdata<n>_ext[7:0] is available.
Receive data control <n> (2 symbols on lane <n>). This signal separates
control and data symbols. The first symbol received is aligned with
rxdatak<n>_ext[0] and the second symbol received is aligned with
rxdata<n>_ext[1]. For the 8 Bit PIPE mode only the single bit signal
rxdatak<n>_ext is available.
Receive valid <n>. This symbol indicates symbol lock and valid data on
rxdata<n>_ext and rxdatak<n>_ext.
1'b0: -6 dB
1'b1: -3.5 dB
OD
margin selection. The PCI Express IP core hard IP sets the
for descriptions of the slightly modified
Description
PCI Express Compiler User Guide
5–57