IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 314

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–8
Figure B–6. RX Retried Transaction and Masked Non-Posted Transaction Waveform
PCI Express Compiler User Guide
Descriptor
Signals
Data
Signals
rx_desc[135:128]
rx_desc[127:64]
rx_data[63:32]
rx_desc[63:0]
rx_data[31:0]
Each virtual channel has a dedicated datapath and associated buffers and no ordering
relationships exist between virtual channels. While one virtual channel may be
temporarily blocked, data flow continues across other virtual channels without
impact. Within a virtual channel, reordering is mandatory only for non-posted
transactions to prevent deadlock. Reordering is not implemented in the following
cases:
In
that it cannot immediately accept. A second transaction (memory write transaction of
one DWORD) is waiting in the receive buffer. Bit 2 of rx_data[63:0] for the memory
write request is set to 1.
In clock cycle three, transmission of non-posted transactions is not permitted for as
long as rx_mask is asserted.
Flow control credits are updated only after a transaction layer packet has been
extracted from the receive buffer and both the descriptor phase and data phase (if
any) have ended. This update happens in clock cycles 8 and 12 in
rx_be[7:0]
rx_mask
rx_abort
Figure
rx_retry
■
■
■
rx_ack
rx_req
rx_ws
rx_dfr
rx_dv
Between traffic classes mapped in the same virtual channel
Between posted and completion transactions
Between transactions of the same type regardless of the relaxed-ordering bit of
the transaction layer packet
clk
B–6, the IP core receives a memory read request transaction of 4 DWORDS
1
2
MEMRD 4 DW
3
valid
valid
0x00
4
5
MEMWR 1DW
6
valid
valid
7
DW 0
0xF0
8
December 2010 Altera Corporation
9
MEMRD 4DW
Figure
Descriptor/Data Interface
valid
valid
0x00
B–6.
11
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