IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 125

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
December 2010 Altera Corporation
PCI Express Reconfiguration Block Signals—Hard IP Implementation
Table 5–18
Table 5–18. LMI Interface
LMI Read Operation
Figure 5–37
next local read or system reset.
Figure 5–37. LMI Read
LMI Write Operation
Figure 5–38
overwritten by this operation. Read-only bits are not affected. LMI write operations
are not recommended for use during normal operation with the exception of AER
header logging.
Figure 5–38. LMI Write
The PCI Express reconfiguration block interface is implemented using an Avalon-MM
slave interface with an 8–bit address and 16–bit data. This interface is available when
you select Enable for the PCIe Reconfig option on the System Settings page of the
MegaWizard interface. You can use this interface to change the value of configuration
registers that are read-only at run time. For a description of the registers available via
this interface refer to the section entitled,
Cancellation.
Signal
lmi_dout
lmi_rden
lmi_wren
lmi_ack
lmi_addr
lmi_din
describes the signals that comprise the LMI interface.
illustrates the read operation. The read data remains available until the
illustrates the LMI write. Only writeable configuration bits are
lmi_addr[11:0]
lmi_addr[11:0]
lmi_dout[31:0]
lmi_din[31:0]
Width
32
1
1
1
12
32
lmi_wren
lmi_rden
lmi_ack
lmi_ack
pld_clk
pld_clk
Dir
O
I
I
O
I
I
Description
Data outputs
Read enable input
Write enable input
Write execution done/read data valid
Address inputs, [1:0] not used
Data inputs
Chapter 13, Reconfiguration and Offset
PCI Express Compiler User Guide
5–41