IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 161

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Reset Hard IP Implementation
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
<variant>_plus.v or .vhd
1
This chapter covers the functional aspects of the reset and clock circuitry for PCI
Express IP core variants created using the MegaWizard Plug-In Manager design flow.
It includes the following sections:
■
■
For descriptions of the available reset and clock signals refer to the following sections
in the
“Clock Signals—Hard IP Implementation” on page
Implementation” on page
Altera provides two options for reset circuitry in the PCI Express hard IP
implementation using the MegaWizard Plug-In Manager. Both options are
automatically created when you generate your IP core. These options are
implemented by following files:
■
■
The reset logic for both of these variants is illustrated by
Refer to
a figure that shows the directories and files created when you generate your core
using the MegaWizard Plug-In Manager.
When you use SOPC Builder to generate the PCI Express IP core, the reset and
calibration logic is included in the IP core variant.
This option partitions the reset logic between the following two plain text files:
■
■
The _plus variant includes all of the logic necessary to initialize the PCI Express IP
core, including the following:
Reset Hard IP Implementation
Clocks
<variant>_plus.v or .vhd—The variant includes the logic for reset and transceiver
calibration as part of the IP core, simplifying system development at the expense
of some flexibility. This file is stored in the <install_dir>/chaining_dma/ directory.
<variant>.v or .vhd—This file does not include reset or calibration logic, giving
you the flexibility to design circuits that meet your requirements. If you select this
method, you can share the channels and reset logic in a single quad with other
protocols which is not possible with _plus option. However, you may find it
challenging to design a reliable solution. This file is stored in the <working_dir>
directory.
<working_dir>/pci_express_compiler-library/altpcie_rs_serdes.v or .vhd—This
file includes the logic to reset the transceiver.
<working_dir>/<variation>_examples/chaining_dma/<variation>_rs_hip.v or
.vhd—This file includes the logic to reset the PCI Express IP core.
Chapter 5, IP Core
“Directory Structure for PCI Express IP Core and Testbench” on page 2–7
Interfaces:
5–23.
“Reset and Link Training Signals” on page
5–23, and
7. Reset and Clocks
Figure
“Clock Signals—Soft IP
PCI Express Compiler User Guide
7–1.
5–24,
for