IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 329

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Descriptor/Data Interface
Figure B–20. TX 64-Bit Memory Read Request Waveform
December 2010 Altera Corporation
Descriptor
Signals
Data
Signals
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
In clock cycle five, the second transaction layer packet is not immediately
acknowledged because of additional overhead associated with a 64-bit address, such
as a separate number and an LCRC. This situation leads to an extra clock cycle
between two consecutive transaction layer packets.
Multiple Wait States Throttle Data Transmission
In this example, the application transmits a 32-bit memory write transaction. Address
bit 2 is set to 0. Refer to
data phases because the IP core implements a small buffer to give maximum
performance during transmission of back-to-back transaction layer packets.
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
clk
1
2
MEMRD64
3
Figure
4
B–21. No wait states are inserted during the first two
MEMWR64
5
6
DW 1
DW 0
7
8
DW 3
DW 2
9
DW 5
DW 4
PCI Express Compiler User Guide
DW 7
DW 6
11
B–23