IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 64

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–6
PCI Express Compiler User Guide
The following sections introduce the functionality of the interfaces shown in
Figure 4–3
Avalon-ST RX Port” on page 5–7
page
RX Datapath
The RX datapath transports data from the transaction layer to the Avalon-ST interface.
A FIFO buffers the RX data from the transaction layer until the streaming interface
accepts it. The adapter autonomously acknowledges all packets it receives from the
PCI Express IP core. The rx_abort and rx_retry signals of the transaction layer
interface are not used. Masking of non-posted requests is partially supported. Refer to
the description of the rx_st_mask<n> signal for further information about masking.
The Avalon-ST RX datapath has a latency range of 3 to 6 pld_clk cycles.
TX Datapath—Arria II GX, Arria II GZ, Cyclone IV GX, HardCopy IV GX, and
Stratix IV GX
The TX datapath transports data from the application's Avalon-ST interface to the
transaction layer. A FIFO buffers the Avalon-ST data until the transaction layer
accepts it for Arria II GX, Arria II GZ, Cyclone IV GX, HardCopy IV GX, and Stratix
IV GX, devices in the hard IP implementation.
If required, TLP ordering should be implemented by the application layer. The TX
datapath provides a TX credit (tx_cred) vector which reflects the number of credits
available. Note that for non–posted requests, this vector accounts for credits pending
in the Avalon-ST adapter. For example, if the tx_cred value is 5, the application layer
has 5 credits available to it. For completions and posted requests, the tx_cred vector
reflects the credits available in the transaction layer of the PCI Express IP core. For
example, for completions and posted requests, if tx_cred is 5, the actual credits
available to the application is (5 – <the number of credits in the adaptor>). You must
account for completion and posted credits which may be pending in the Avalon-ST
adapter. You can use the read and write FIFO pointers and the FIFO empty flag to
track packets as they are popped from the adaptor FIFO and transferred to the
transaction layer.
TLP Reordering—Arria II GX, HardCopy IV GX, and Stratix IV GX Devices
For Arria II GX, HardCopy IV GX, and Stratix IV GX devices, applications that use
the non-posted tx_cred signal must never send more packets than tx_cred allows.
While the IP core always obeys PCI Express flow control rules, the behavior of the
tx_cred signal itself is unspecified if the credit limit is violated. When evaluating
tx_cred, the application must take into account TLPs that are in flight, and not yet
reflected in tx_cred.The following is the recommended procedure. Note that in Step
3, the user exhausts tx_cred before waiting for more credits to free. This is a required
step.
1. No TLPs have been issued by the application.
2. The application waits for tx_cred to indicate that credits are available.
3. The application sends as many TLPs as are allowed by tx_cred. For example, if
4. The application waits for the TLPs to cross the Avalon-ST TX interface.
tx_cred indicates 3 credits of non-posted headers are available, the application
sends 3 non-posted TLPs, then stops.
5–13.
and
Figure
4–4. For more detailed information, refer to
and
“64-, 128-, or 256-Bit Avalon-ST TX Port” on
December 2010 Altera Corporation
Chapter 4: IP Core Architecture
“64-, 128-, or 256-Bit
Application Interfaces