IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 229

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
1
This chapter introduces the root port or endpoint design example including a
testbench, BFM, and a test driver module. When you create a PCI Express function
variation using the MegaWizard Plug-In Manager flow as described in
Getting
customized to your variation. This design example is not generated when using the
SOPC Builder flow.
When configured as an endpoint variation, the testbench instantiates a design
example and a root port BFM, which provides the following functions:
■
■
The testbench uses a test driver module, altpcietb_bfm_driver_chaining, to exercise
the chaining DMA of the design example. The test driver module displays
information from the endpoint configuration space registers, so that you can correlate
to the parameters you specified using the parameter editor.
When configured as a root port, the testbench instantiates a root port design example
and an endpoint model, which provides the following functions:
■
■
The testbench uses a test driver module, altpcietb_bfm_driver_rp, to exercise the
target memory and DMA channel in the endpoint BFM. The test driver module
displays information from the root port configuration space registers, so that you can
correlate to the parameters you specified using the parameter editor. The endpoint
model consists of an endpoint variation combined with the chaining DMA
application described above.
PCI Express link monitoring and error injection capabilities are limited to those
provided by the IP core’s test_in and test_out signals. The following sections
describe the testbench, the design example, root port and endpoint BFMs in detail.
The Altera testbench and root port or endpoint BFM provide a simple method to do
basic testing of the application layer logic that interfaces to the variation. However,
the testbench and root port BFM are not intended to be a substitute for a full
verification environment. To thoroughly test your application, Altera suggests that
you obtain commercially available PCI Express verification IP and tools, or do your
own extensive hardware testing or both.
A configuration routine that sets up all the basic configuration registers in the
endpoint. This configuration allows the endpoint application to be the target and
initiator of PCI Express transactions.
A VHDL/Verilog HDL procedure interface to initiate PCI Express transactions to
the endpoint.
A configuration routine that sets up all the basic configuration registers in the root
port and the endpoint BFM. This configuration allows the endpoint application to
be the target and initiator of PCI Express transactions.
A Verilog HDL procedure interface to initiate PCI Express transactions to the
endpoint BFM.
Started, the PCI Express compiler generates a design example and testbench
15. Testbench and Design Example
PCI Express Compiler User Guide
Chapter 2,