IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 227

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 14: External PHYs
External PHY Constraint Support
Table 14–4. External PHY Support Matrix
External PHY Constraint Support
December 2010 Altera Corporation
Arria GX
Stratix II GX
Stratix IV GX
TI XIO1100
NXP PX1011A
Custom
PHY Type
(pclk only)
■
■
Table 14–4
interface, the table lists the allowed lane widths.
The TI XIO1100 device has some additional control signals that need to be driven by
your design. These can be statically pulled high or low in the board design, unless
additional flexibility is needed by your design and you want to drive them from the
Altera device. These signals are shown in the following list:
■
■
■
The PCI Express Compiler supports various location and timing constraints. When
you parameterize and generate your IP core, the Quartus II software creates a Tcl file
that runs when you compile your design. The Tcl file incorporates the following
constraints that you specify when you parameterize and generate during
parameterization.
■
■
■
■
Altera also provides an SDC file with the same constraints. The TimeQuest timing
analyzer uses the SDC file.
16-bit
×1, ×4
SDR
-
-
-
-
-
Select the specific PHY.
Select the type of interface to the PHY by selecting Custom in the PHY type list.
Several PHYs have multiple interface modes.
P1_SLEEP must be pulled low. The PCI Express IP core requires the refclk (RX_CLK
from the XIO1100) to remain active while in the P1 powerdown state.
DDR_EN must be pulled high if your variation of the PCI Express IP core uses the 8-
bit DDR (w/TXClk) mode. It must be pulled low if the 16-bit SDR (w/TXClk) mode
is used.
CLK_SEL must be set correctly based on the reference clock provided to the
XIO1100. Consult the XIO1100 data sheet for specific recommendations.
refclk (pclk from the PHY) frequency constraint (125 MHz or 250 MHz)
Setup and hold constraints for the input signals
Clock-to-out constraints for the output signals
I/O interface standard
(w/TXClk)
summarizes the PHY support matrix. For every supported PHY type and
16-bit
×1, ×4
SDR
×1
-
-
-
-
(pclk only)
×1, ×4
8-bit
DDR
-
-
-
-
-
Allowed Interfaces and Lanes
(w/TXClk)
×1, ×4
8-bit
DDR
-
-
-
-
-
DDR/SDR
(w/TXClk)
8-bit
×1
-
-
-
-
-
(pclk only)
×1, ×4
8-bit
SDR
-
-
-
-
-
PCI Express Compiler User Guide
(w/TXClk)
×1, ×4
8-bit
SDR
×1
-
-
-
-
×1, ×4, ×8
×1, ×4, ×8
Interface
Serial
×1, ×4
-
-
-
14–11