IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 187

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 9: Optional Features
Lane Initialization and Reversal
Lane Initialization and Reversal
Table 9–4. Lane Assignments without Reversal
Table 9–5. Lane Assignments with Reversal
December 2010 Altera Corporation
Lane Number
×8 IP core
×4 IP core
×1 IP core
Lane
assignments
Core Config
Slot Size
1
7:0,6:1,5:2,4:3,3:4,
2:5,1:6,0:7
■
Some time adjustment may be necessary if one or more switches are located between
the endpoint and the root port.
To maximize performance, Altera recommends that you set L0s and L1 acceptable
latency values to their minimum values.
Connected PCI Express components need not support the same number of lanes. The
×4 and ×8 IP core in both soft and hard variations support initialization and operation
with components that have 1, 2, or 4 lanes. The ×8 IP core in both soft and hard
variations supports initialization and operation with components that have 1, 2, 4, or
8 lanes.
The hard IP implementation includes lane reversal, which permits the logical reversal
of lane numbers for the ×1, ×2, ×4, and ×8 configurations. The Soft IP implementation
does not support lane reversal but interoperates with other PCI Express endpoints or
root ports that have implemented lane reversal. Lane reversal allows more flexibility
in board layout, reducing the number of signals that must cross over each other when
routing the PCB.
Table 9–4
Table 9–5
8
For L1, software calculates the L1 exit latency of each link between the endpoint
and the root port, and compares the maximum value with the endpoint’s
acceptable latency. For example, for an endpoint connected to a root port, if the
root port’s L1 exit latency is 1.5 µs and the endpoint’s L1 exit latency is 4 µs, and
the endpoint acceptable latency is 2 µs, the exact L1 exit latency of the link is 4 µs
and software will probably not enable the entry to L1.
—
—
7
7
summarizes the lane assignments for normal configuration.
summarizes the lane assignments with lane reversal.
3:4,2:5,
1:6,0:7
8
4
—
—
6
6
1:6,
0:7
2
—
—
5
5
0:7
1
7:0,6:1,
5:2,4:3
8
—
—
4
4
3:0,2:1,
1:2,0:3
4
—
4
3
3
3
3:0,
2:1
2
—
2
2
2
3:0
PCI Express Compiler User Guide
1
7:0
8
—
1
1
1
3:0
4
1
1:0
2
0
0
0
0
0:0
9–5
1