IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 19

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: Datasheet
General Description
Table 1–5. PCIe Hard IP Configurations for the PCIe Compiler in the Quartus II Software in Version 10.1 (Part 2 of 2)
Table 1–6. PCI Express Compiler Release Information
Figure 1–3. PCI Express Application with a Single Root Port and Endpoint
December 2010 Altera Corporation
Cyclone IV GX
Stratix IV GX
Note to
(1) For devices that do not offer a ×2 initial configuration, you can use a ×4 configuration with the upper two lanes left unconnected at the device
(2) The ×8 support uses a 128-bit bus at 125 MHz.
Arria II GX
Arria II GZ
Cyclone IV GX
Stratix IV GX
HardCopy IV GX–Gen2 ×8
HardCopy IV GX–all other modes
Note to
(1) You can restrict Stratix IV GX Gen2 ×8 designs to operate with HardCopy IV GX compatible buffer sizes by selecting HardCopy IV GX for the
pins. The link will negotiate to ×2 if the attached device is ×2 native or capable of negotiating to ×2.
PHY type
Table
Table
Device
Devices Family
parameter.
1–5:
1–6:
Altera FPGA with Embedded PCIe
Hard IP Block
User Application
Table 1–6
size for device families that include the hard IP implementation. You can find these
parameters on the Buffer Setup page of the parameter editor.
The PCI Express Compiler allows you to select IP cores that support ×1, ×2, ×4, or ×8
operation
applications. You can use the MegaWizard Plug-In Manager or SOPC Builder to
customize the IP core.
two PCI Express IP cores, one configured as a root port and the other as an endpoint.
2.5
5.0
2.5
5.0
Link Rate (Gbps)
Logic
lists the Total RX buffer space, Retry buffer size, and Maximum Payload
(Table 1–7 on page
Total RX Buffer Space
Hard IP
PCIe
16 KBytes
16 KBytes
16 KBytes
4 KBytes
4 KBytes
8 KBytes
RP
Figure 1–3
yes
yes
yes
no
×1
PCI Express Link
1–10) that are suitable for either root port or endpoint
shows a relatively simple application that includes
×2
yes
no
no
no
Retry Buffer
EP
Hard IP
Altera FPGA with Embedded PCIe
Hard IP Block
16 KBytes
16 KBytes
16 KBytes
(1)
2 KBytes
2 KBytes
8 KBytes
PCIe
User Application
yes
yes
no
no
×4
Logic
PCI Express Compiler User Guide
Max Payload Size
256 Bytes
256 Bytes
2 KBytes
2 KBytes
1 KBytes
2 KBytes
no
no
no
no
×8
1–9