IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 335

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Incremental Compile Module for Descriptor/Data Examples
Figure B–24. ICM Block Diagram
December 2010 Altera Corporation
app_int_sts_ack_icm
msi_stream_ready0
(streaming interface )
To user application
pex_msi_num_icm
msi_stream_data0
msi_stream_valid0
rx_stream_ready0
rx_stream_mask0
tx_stream_ready0
tx_stream_mask0
tx_stream_mask0
cfg_tcvcmap_icm
rx_stream_valid0
rx_stream_data0
tx_stream_valid0
tx_stream_data0
tx_stream_cred0
cpl_pending_icm
app_int_sts_icm
cfg_busdev_icm
cfg_devcsr_icm
cfg_msicsr_icm
cfg_linkcsr_icm
test_out_icm
cpl_err_icm
ICM Block Diagram
Figure B–24
The ICM comprises four main sections:
■
■
■
■
All signals between the PCI Express IP core and the user application are registered by
the ICM. The design example implements the ICM interface with one virtual channel.
For multiple virtual channels, duplicate the RX and TX Avalon-ST interfaces for each
virtual channel.
“RX Datapath”
“TX Datapath”
“MSI Datapath”
“Sideband Datapath”
Reg
Reg
shows the ICM block diagram.
Reg
Reg
O
F
F
I
Incremental Compile Module (ICM)
ICM Sideband
Avalon-ST Rx
Conversion
NP Bypass
Avalon-ST MSI
Avalon-ST Tx Conversion
Conversion
Read Control
Arbitration
Msg Handler
(ack & drop
messages)
ICM Tx
ICM Rx
Instantiate
channel
one per
1'b0
virtual
PCI Express Compiler User Guide
Transaction Layer
To PCI Express
rx_req0
rx_desc0
rx_dfr0
rx_dv0
rx_data0
rx_ack0
rx_ws0
rx_retry0
rx_abort0
rx_mask0
tx_req0
tx_desc0
tx_dfr0
tx_dv0
tx_data0
tx_err0
cpl_err0
cpl_pending0
tx_ack0
tx_ws0
tx_cred0
app_msi_num
app_msi_req
app_msi_tc
app_msi_ack
cpl_pending
cpl_err
pex_msi_num
app_int_sts
app_int_sts_ack
cfg_msicsr
cfg_busdev
cfg_devcsr
cfg_linkcsr
cfg_tcvcmap
test_out
B–29