IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 268

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

15–40
Table 15–31. ebfm_cfg_rp_ep Procedure (Part 2 of 2)
Table 15–32. ebfm_cfg_decode_bar Procedure
PCI Express Compiler User Guide
Location
Syntax
Arguments
BFM Shared Memory Access Procedures
ep_bus_num
ep_dev_num
rp_max_rd_req_size
display_ep_config
addr_map_4GB_limit
altpcietb_bfm_configure.v or altpcietb_bfm_configure.vhd
ebfm_cfg_decode_bar(bar_table, bar_num, log2_size, is_mem, is_pref, is_64b)
bar_table
bar_num
log2_size
is_mem
is_pref
is_64b
ebfm_cfg_decode_bar Procedure
The ebfm_cfg_decode_bar procedure analyzes the information in the BAR table for
the specified BAR and returns details about the BAR attributes.
The following procedures and functions are available in the VHDL file
altpcietb_bfm_shmem.vhd or in the Verilog HDL include file
altpcietb_bfm_shmem.v that uses the module
altpcietb_bfm_shmem_common.v, instantiated at the top level of the testbench.
These procedures and functions support accessing the BFM shared memory.
All VHDL arguments are subtype natural and are input-only unless specified
otherwise. All Verilog HDL arguments are type integer and are input-only unless
specified otherwise.
Address of the endpoint bar_table structure in BFM shared memory.
BAR number to analyze.
This argument is set by the procedure to the log base 2 of the size of the BAR. If the BAR is
not enabled, this argument will be set to 0.
The procedure sets this argument to indicate if the BAR is a memory space BAR (1) or I/O
Space BAR (0).
The procedure sets this argument to indicate if the BAR is a prefetchable BAR (1) or non-
prefetchable BAR (0).
The procedure sets this argument to indicate if the BAR is a 64-bit BAR (1) or 32-bit BAR
(0). This is set to 1 only for the lower numbered BAR of the pair.
PCI Express bus number of the target device. This number can be any value
greater than 0. The root port uses this as its secondary bus number.
PCI Express device number of the target device. This number can be any value.
The endpoint is automatically assigned this value when it receives its first
configuration transaction.
Maximum read request size in bytes for reads issued by the root port. This
parameter must be set to the maximum value supported by the endpoint
application layer. If the application layer only supports reads of the
MAXIMUM_PAYLOAD_SIZE, then this can be set to 0 and the read request size
will be set to the maximum payload size. Valid values for this argument are 0,
128, 256, 512, 1,024, 2,048 and 4,096.
When set to 1 many of the endpoint configuration space registers are displayed
after they have been initialized, causing some additional reads of registers that
are not normally accessed during the configuration process such as the Device
ID and Vendor ID.
When set to 1 the address map of the simulation system will be limited to 4
GBytes. Any 64-bit BARs will be assigned below the 4 GByte limit.
Chapter 15: Testbench and Design Example
December 2010 Altera Corporation
BFM Procedures and Functions