IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 115

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–12. Interrupt Signals for Root Ports
Table 5–13. Configuration Space Signals (Hard IP Implementation) (Part 1 of 2)
December 2010 Altera Corporation
int_status[3:0]
aer_msi_num[4:0]
pex_msi_num[4:0]
serr_out
Signal
tl_cfg_add
tl_cfg_ctl
PCI Express Interrupts for Root Ports
Configuration Space Signals—Hard IP Implementation
Signal
Width Dir Description
4
32
Table 5–12
The hard IP implementation of the configuration space signals is the same for
Arria II GX, Cyclone IV GX, HardCopy IV, and Stratix IV GX. For Stratix V devices
refer to
Arria II GX, Cyclone IV GX, HardCopy IV, and Stratix IV GX
The configuration space signals provide access to some of the control and status
information available in the configuration space registers; these signals provide access
to unused registers that are labeled reserved in the
Revision
space from the application layer, you must synchronize to the application layer clock.
Table 5–13
available in the hard IP implementation. Refer to Chapter 6 of the
Specification Revision 2.0
I/O
O
O
I
I
0
0
“Stratix V Hard IP Implementation” on page
2.0. This interface is synchronous to core_clk. To access the configuration
hese signals drive legacy interrupts to the application layer using a TLP of type Message
Interrupt as follows:
■
■
■
■
Advanced error reporting (AER) MSI number. This signal is used by AER to determine the
offset between the base message data and the MSI to send. This signal is only available
for root port mode.
Power management MSI number. This signal is used by power management and/or hot
plug to determine the offset between the base message interrupt number and the message
interrupt number to send through MSI.
System Error: This signal only applies to hard IP root port designs that report each system
error detected by the IP core, assuming the proper enabling bits are asserted in the root
control register and the device control register. If enabled, serr_out is asserted for a
single clock cycle when a system error occurs. System errors are described in the
Express Base Specification 1.1 or
describes the signals available to a root port to handle interrupts.
describes the configuration space interface and hot plug signals that are
Address of the register that has been updated. This address space is described in
Table 5–15 on page
tl_cfg_ctl.
The tl_cfg_ctl signal is multiplexed and contains the contents of the configuration space
registers as shown in this table. This register carries data that updates every 8
core_clk cycles.
int_status[0]: interrupt signal A
int_status[1]: interrupt signal B
int_status[2]: interrupt signal C
int_status[3]: interrupt signal D
for more information about the hot plug signals.
5–36. The information updates every 8 core_clks along with
2.0. in the root control register.
Description
PCI Express Base Specification
5–34.
PCI Express Compiler User Guide
PCI Express Base
PCI
5–31