IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 91

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–2. 64-, 128-, or 256-Bit Avalon-ST RX Datapath (Part 1 of 2)
December 2010 Altera Corporation
Signal
rx_st_ready<n>
rx_st_valid<n>
rx_st_data<n>
rx_st_sop<n>
rx_st_eop<n>
rx_st_empty<n>
rx_st_err<n>
rx_st_mask<n>
64-, 128-, or 256-Bit Avalon-ST RX Port
(1) (2)
(2)
Table 5–2
Width Dir
1
1
64
128,
256
1
1
1
1
1
describes the signals that comprise the Avalon-ST RX Datapath.
I
O
O
O
O
O
O
I
ready
valid
data
start of
packet
end of
packet
empty
error
component
specific
Avalon-ST
Component Specific Signals
Type
Description
Indicates that The application is ready to accept data. The
application deasserts this signal to throttle the data stream.
Clocks rx_st_data<n> into application. Deasserts within 3
clocks of rx_st_ready<n> deassertion and reasserts within 3
clocks of rx_st_ready<n> assertion if more data is available
to send. rx_st_valid can be deasserted between the
rx_st_sop and rx_st_eop eve if rx_st_ready is asserted.
Receive data bus. Refer to
the mapping of the transaction layer’s TLP information to
rx_st_data. Refer to
position of the first payload dword depends on whether the TLP
address is qword aligned. The mapping of message TLPs is the
same as the mapping of transaction layer TLPs with 4 dword
headers. When using a 64-bit Avalon-ST bus, the width of
rx_st_data<n> is 64. When using a 128-bit Avalon-ST bus,
the width of rx_st_data<n> is 128. When using a 256-bit
Avalon-ST bus, the width or rx_st_data is 256 bits.
Indicates that this is the first cycle of the TLP.
Indicates that this is the last cycle of the TLP.
Indicates that the TLP ends in the lower 64 bits of rx_st_data.
Valid only when rx_st_eop<n> is asserted. This signal only
applies to 128-bit mode in the hard IP implementation.
Indicates that there is an uncorrectable ECC error in the core’s
internal RX buffer of the associated VC. When an uncorrectable
ECC error is detected, rx_st_err is asserted for at least 1
cycle while rx_st_valid is asserted. If the error occurs before
the end of a TLP payload, the packet may be terminated early
with an rx_st_eop and with rx_st_valid deasserted on the
cycle after the eop. This signal is only active for the hard IP
implementations when ECC is enabled.
This signal is not available for the hard IP implementation in
Arria II GX devices.
Application asserts this signal to tell the IP core to stop sending
non-posted requests. This signal does not affect non-posted
requests that have already been transferred from the
transaction layer to the Avalon-ST Adaptor module. This signal
can be asserted at any time. The total number of non-posted
requests that can be transferred to the application after
rx_st_mask is asserted is not more than 26 for 128-bit mode
and not more than 14 for 64-bit mode.
Figure 5–14
Figure 5–6
for the timing. Note that the
PCI Express Compiler User Guide
through
Figure 5–13
for
5–7