IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 318

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–12
Table B–6. Standard TX Descriptor Phase Signals (Part 1 of 2)
PCI Express Compiler User Guide
tx_req<n>
tx_desc<n>[127:0]
Transmit Operation Interface Signals
Signal
(1)
1
The transmit interface is established per initialized virtual channel and is based on
two independent buses, one for the descriptor phase (tx_desc[127:0]) and one for
the data phase (tx_data[63:0]). Every transaction includes a descriptor. A descriptor
is a standard transaction layer packet header as defined by the
Specification 1.0a, 1.1 or 2.0
transaction layer packet group as described in the following section. Only transaction
layer packets with a normal data payload include one or more data phases.
Transmit Datapath Interface Signals
The IP core assumes that transaction layer packets sent by the application layer are
well-formed; the IP core does not detect malformed transaction layer packets sent by
the application layer.
Transmit datapath signals can be divided into the following two groups:
■
■
In the following tables, transmit interface signal names suffixed with <n> are for
virtual channel <n>. If the IP core implements additional virtual channels, there are
an additional set of signals suffixed with the virtual channel number.
Table B–6
Descriptor phase signals
Data phase signals
I/O
I
I
describes the standard TX descriptor phase signals.
Transmit request. This signal must be asserted for each request. It is always asserted
with the tx_desc[127:0] and must remain asserted until tx_ack is asserted. This
signal does not need to be deasserted between back-to-back descriptor packets.
Transmit descriptor bus. The transmit descriptor bus, bits [127:0] of a transaction, can
include a 3 or 4 DWORDS PCI Express transaction header. Bits have the same meaning
as a standard transaction layer packet header as defined by the
Specification Revision 1.0a, 1.1 or
the tx_desc bus, byte 1 of the header occupies bits [119:112], and so on, with byte 15
in bits [7:0]. Refer to
the header formats.
The following bits have special significance:
■
■
■
■
■
tx_desc[2] or tx_desc[34] indicate the alignment of data on tx_data.
tx_desc[2] (64-bit address) when 0: The first DWORD is located on
tx_data[31:0].
tx_desc[34] (32-bit address) when 0: The first DWORD is located on bits
tx_data[31:0].
tx_desc[2] (64-bit address) when1: The first DWORD is located on bits
tx_data[63:32].
tx_desc[34] (32-bit address) when 1: The first DWORD is located on bits
tx_data[63:32].
with the exception of bits 126 and 127, which indicate the
Appendix A, Transaction Layer Packet (TLP) Header Formats
2.0. Byte 0 of the header occupies bits [127:120] of
Description
December 2010 Altera Corporation
PCI Express Base
PCI Express Base
Descriptor/Data Interface
Chapter :
for