IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 338

IP CORE Renewal Of IP-PCIE/1

IPR-PCIE/1

Manufacturer Part Number
IPR-PCIE/1
Description
IP CORE Renewal Of IP-PCIE/1
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-PCIE/1

Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x1 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
B–32
Table B–14. Application-Side RX Signals
Figure B–25. RX Interface Timing Diagram
PCI Express Compiler User Guide
rx_st_valid0
rx_st_data0
rx_st_ready0
rx_stream_mask0
Signal
rx_stream_ready0
rx_stream_valid0
rx_eop_flag
rx_sop_flag
rx_desc0
rx_data0
[81:74]
[73]
[72]
[71:64]
[63:0]
RX Ports
Table B–14
Figure B–25
Bits
clk
1
Byte Enable bits
rx_sop_flag
rx_eop_flag
Bar bits
rx_desc/rx_data
2
Subsignals
describes the application-side ICM RX signals.
shows the application-side RX interface timing diagram.
3
4
Other RX Interface Signals
Clocks rx_st_data into the application. The application must accept the
data when rx_st_valid is high.
Byte-enable bits. These are valid on the data (3rd to last) cycles of the
packet.
When asserted, indicates that this is the first cycle of the packet.
When asserted, indicates that this is the last cycle of the packet.
BAR bits. These are valid on the 2nd cycle of the packet.
Multiplexed rx_desc/rx_data bus
1st cycle – rx_desc0[127:64]
2nd cycle – rx_desc0[63:0]
3rd cycle – rx_data0 (if any)
Refer to
rx_data0.
The application asserts this signal to indicate that it can accept more
data. The ICM responds 3 cycles later by deasserting rx_st_valid.
Application asserts this to tell the IP core to stop sending non-posted
requests to the ICM. Note: This does not affect non-posted requests that
the IP core already passed to the ICM.
Interface Signals
5
Table B–1 on page B–3
6
desc_hi desc_lo data0
ICM_response_time
7
8
Incremental Compile Module for Descriptor/Data Examples
9
data1
Description
for information on rx_desc0 and
10
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