IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 133

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-MM Application Interface
Table 5–24. Signal Groups in the PCI Express Variants—Avalon-MM Interface
Table 5–25. Avalon-MM CRA Slave Interface Signals
December 2010 Altera Corporation
Signal Group
Avalon-MM CRA Slave
Avalon-MM RX Master
Avalon-MM TX Slave
Clock
Reset and Status
Transceiver Control
Serial
Pipe
Test
CraIrq_o
CraReadData_o[31:0]
CraWaitRequest_o
CraAddress_i[11:0]
CraByteEnable_i[3:0]
CraChipSelect_i
CraRead_i
CraWrite_i
CraWriteData_i[31:0]
Signal SOPC Builder
32-Bit Non-bursting Avalon-MM CRA Slave Signals
f
Table 5–24
each.
The PCI Express IP cores with Avalon-MM interface implement the Avalon-MM
which is described in the
information about the Avalon-MM protocol, including timing diagrams.
This optional port for the full-featured IP core allows upstream PCI Express devices
and external Avalon-MM masters to access internal control and status registers.
Table 5–25
Featured
Full
v
v
v
v
v
v
v
v
v
I/O
O
O
O
I
I
I
I
I
I
lists the interfaces for these IP cores with links to the sections that describe
describes the CRA slave ports.
Irq
Readdata
Waitrequest Wait request to hold off more requests
Address
Byteenable
Chipselect
Read
Write
Writedata
Completer
Type
Only
v
v
v
v
v
v
v
—
—
Physical and Test
Avalon Interface Specifications.
Interrupt request. A port request for an Avalon-MM interrupt.
Read data lines
An address space of 16,384 bytes is allocated for the control registers.
Avalon-MM slave addresses provide address resolution down to the
width of the slave data bus. Because all addresses are byte addresses,
this address logically goes down to bit 2. Bits 1 and 0 are 0.
Byte enable
Chip select signal to this slave
Read enable
Write request
Write data
“32-Bit Non-bursting Avalon-MM CRA Slave Signals” on page 5–49
“RX Avalon-MM Master Signals” on page 5–50
“64-Bit Bursting TX Avalon-MM Slave Signals” on page 5–50
“Clock Signals” on page 5–51
“Reset and Status Signals” on page 5–52
“Transceiver Control” on page 5–53
“Serial Interface Signals” on page 5–55
“PIPE Interface Signals” on page 5–56
“Test Signals” on page 5–58
Logical
Description
Description
Refer to this specification for
PCI Express Compiler User Guide
5–49