IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 78

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–20
PCI Express Compiler User Guide
As an example,
Table 4–2. Valid Byte Enable Configurations
Avalon-MM-to-PCI Express Read Completions
The PCI Express Avalon-MM bridge converts read response data from the external
Avalon-MM slave to PCI Express completion packets and sends them to the
transaction layer.
A single read request may produce multiple completion packets based on the
Maximum Payload Size and the size of the received read request. For example, if the
read is 512 bytes but the Maximum Payload Size 128 bytes, the bridge produces four
completion packets of 128 bytes each. The bridge does not generate out-of-order
completions. You can specify the Maximum Payload Size parameter on the Buffer
Setup page of the MegaWizard Plug-In Manager interface. Refer to
Parameters” on page
PCI Express-to-Avalon-MM Address Translation
The PCI Express address of a received request packet is translated to the Avalon-MM
address before the request is sent to the system interconnect fabric. This address
translation proceeds by replacing the MSB bits of the PCI Express address with the
value from a specific translation table entry; the LSB bits remain unchanged. The
number of MSB bits to replace is calculated from the total memory allocation of all
Avalon-MM slaves connected to the RX Master Module port. Six possible address
Byte Enable Value
4’b1111
4’b0011
4’b1100
4’b0001
4’b0010
4’b0100
4’b1000
Table 4–2
3–10.
Description
Write full 32 bits
Write the lower 2 bytes
Write the upper 2 bytes
Write byte 0 only
Write byte 1 only
Write byte 2 only
Write byte 3 only
gives the byte enables for 32-bit data.
December 2010 Altera Corporation
Chapter 4: IP Core Architecture
PCI Express Avalon-MM Bridge
“Buffer Setup