IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 323

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Descriptor/Data Interface
Figure B–12. TX 64-Bit Completion with Data Transaction of Eight DWORD Waveform
December 2010 Altera Corporation
Descriptor
Signals
Data
Signals
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
Transaction Examples Using Transmit Signals
This section provides the following examples that illustrate how transaction signals
interact:
■
■
■
■
■
■
■
■
Ideal Case Transmission
In the ideal case, the descriptor and data transfer are independent of each other, and
can even happen simultaneously. Refer to
completion transaction of eight dwords. Address bit 2 is set to 0.
In clock cycle 4, the first data phase is acknowledged at the same time as transfer of
the descriptor.
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
Ideal Case Transmission
Transaction Layer Not Ready to Accept Packet
Possible Wait State Insertion
Transmit Request Can Remain Asserted Between Transaction Layer Packets
Priority Given Elsewhere
Transmit Request Can Remain Asserted Between Transaction Layer Packets
Multiple Wait States Throttle Data Transmission
Error Asserted and Transmission Is Nullified
clk
1
2
3
CPLD
4
DW1
DW0
Figure
5
DW3
DW2
B–12. The IP core transmits a
6
DW5
DW4
7
DW7
DW6
PCI Express Compiler User Guide
8
9
B–17