IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 293

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 16: SOPC Builder Design Example
Simulate the SOPC Builder System
December 2010 Altera Corporation
f
SOPC Builder creates IP functional simulation models for all the system components.
The IP functional simulation models are the .vo or .vho files generated by SOPC
Builder in your project directory.
For more information about IP functional simulation models, refer to
Designs
The SOPC Builder-generated top-level file also integrates the simulation modules of
the system components and testbenches (if available), including the PCI Express
testbench. The Altera-provided PCI Express testbench simulates a single link at a
time. You can use this testbench to verify the basic functionality of your PCI Express
Compiler system. The default configuration of the PCI Express testbench is
predefined to run basic PCI Express configuration transactions to the PCI Express
device in your SOPC Builder generated system. You can edit the PCI Express
testbench altpcietb_bfm_driver.v or altpcietb_bfm_driver.vhd file to add other PCI
Express transactions, such as memory read (MRd) and memory write (MWr).
For more information about the PCI Express BFM, refer to
Design
For this design example, perform the following steps:
1. Before simulating the system, if you are running the Verilog HDL design example,
2. Choose Programs > ModelSim-Altera><ver> ModelSim (Windows Start menu)
3. To run the script, type the following command at the simulator command prompt:
4. To compile all the files and load the design, type the following command at the
edit the altpcietb_bfm_driver.v file in the
c:\sopc_pci\pci_express_compiler_examples\sopc\testbench directory to
enable target and DMA tests. Set the following parameters in the file to one:
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If you are running the VHDL design example, edit the altpcietb_bfm_driver.vhd
in the c:\sopc_pci\pci_express_compiler_examples\sopc\testbench directory to
set the following parameters to one.
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1
to start the ModelSim-Altera simulator. In the simulator change your working
directory to c:\sopc_pcie\pcie_top_sim.
simulator prompt:
parameter RUN_TGT_MEM_TST = 1;
parameter RUN_DMA_MEM_TST = 1;
source setup_sim.do r
s r
Example.
in volume 3 of the Quartus II Handbook.
RUN_TGT_MEM_TST : std_logic := '1';
RUN_DMA_MEM_TST : std_logic := '1';
The target memory and DMA memory tests in the altpcietb_bfm_driver.v
file enabled by these parameters only work with the SOPC Builder system
as specified in this chapter. When designing an application, modify these
tests to match your system.
Chapter 15, Testbench and
PCI Express Compiler User Guide
Simulating Altera
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