EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 112

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
Figure 6–6. Clkena Implementation - Output Enable
6–12
Cyclone III Device Handbook, Volume 1
clkena
clk_out
clkin
Figure 6–6
clkena signal is sampled on the falling edge of the clock (clkin).
This feature is useful for applications that require a low power or sleep
mode.
The clkena signal can also disable clock outputs if the system is not
tolerant to frequency overshoot during PLL resynchronization.
Altera recommends using the clkena signals when switching the clock
source to the PLLs or the global clock network. The recommended
sequence is:
1.
2.
3.
Disable the primary output clock by de-asserting the clkena signal.
Switch to the secondary clock using the dynamic select signals of the
clock control block.
Allow some clock cycles of the secondary clock to pass before
re-asserting the clkena signal. The exact number of clock cycles
you need to wait before enabling the secondary clock is design
dependent. You can build custom logic to ensure glitch-free
transition when switching between different clock sources.
shows the waveform example for a clock output enable. The
Altera Corporation- Preliminary
March 2007