EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 254

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Configuring Cyclone III Devices
10–18
Cyclone III Device Handbook, Volume 1
In AS configuration scheme, the serial configuration device latches input
and control signals on the rising edge of DCLK and drives out
configuration data on the falling edge. Cyclone III devices drive out
control signals on the falling edge of DCLK and latch configuration data
on the falling edge of DCLK.
1
In configuration mode, the Cyclone III device enables the serial
configuration device by driving the FLASH_nCE output pin low, which
connects to the chip select (nCS) pin of the configuration device. The
Cyclone III device uses the serial clock (DCLK) and serial data output
(DATA[1]) pins to send operation commands and/or read address
signals to the serial configuration device. The configuration device
provides data on its serial data output (DATA) pin, which connects to the
DATA[0] input of the Cyclone III device.
After all configuration bits are received by the Cyclone III device, it
releases the open-drain CONF_DONE pin, which is pulled high by an
external 10 KΩ resistor. Initialization begins only after the CONF_DONE
signal reaches a logic high level. All AS configuration pins (DATA[0],
DCLK, FLASH_nCE, and DATA[1]) have weak internal pull-up resistors
that are always active. After configuration, these pins are set as input
tri-stated and are driven high by the weak internal pull-up resistors. The
CONF_DONE pin must have an external 10 KΩ pull-up resistor in order for
the device to initialize.
In Cyclone III devices, the initialization clock source is either the 10 MHz
(typical) internal oscillator (separate from the active serial internal
oscillator) or the optional CLKUSR pin. By default, the internal oscillator
is the clock source for initialization. If the internal oscillator is used, the
Cyclone III device provides itself with enough clock cycles for proper
initialization. The advantage of using the internal oscillator is you do not
need to send additional clock cycles from an external source to the
CLKUSR pin during the initialization stage. Additionally, you can use the
CLKUSR pin as a user I/O pin.
You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization with the CLKUSR option. Using the
CLKUSR pin allows you to control when your device enters user mode.
The device can be delayed from entering user mode for an indefinite
amount of time. The Enable user-supplied start-up clock (CLKUSR)
option can be turned on in the Quartus II software from the General tab
of the Device & Pin Options dialog box. When you Enable the user
The FLASH_nCE pin and DATA[1] pin are dual-purpose I/O
pins. The FLASH_nCE pin functions as the nCSO pin in the AS
configuration scheme. The DATA[1] pin functions as the ASDO
pin in the AS configuration scheme.
Altera Corporation-Preliminary
March 2007