EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 307

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
TDI
TDO
Pin Name
Table 10–14. Dedicated JTAG Pins
Test data input
Test data output
Pin Type
f
For more information on JTAG boundary-scan testing, refer to the
following documents:
■
■
Cyclone III devices are designed such that JTAG instructions have
precedence over any device configuration modes. Therefore, JTAG
configuration can take place without waiting for other configuration
modes to complete. For example, if you attempt JTAG configuration of
Cyclone III devices during PS configuration, PS configuration terminates
and JTAG configuration begins. If the Cyclone III MSEL pins are set to AS
mode, the Cyclone III device does not output a DCLK signal when JTAG
configuration takes place.
1
The four required pins for a device operating in JTAG mode are TDI, TDO,
TMS, and TCK. The TCK pin has an internal weak pull-down resistor, while
the TDI, and TMS pins have weak internal pull-up resistors (typically
25 k
JTAG input pins are powered by the V
only LVTTL I/O standard. All user I/O pins are tri-stated during JTAG
configuration.
1
Serial input pin for instructions as well as test and programming data. Data is
shifted in on the rising edge of
board, the JTAG circuitry can be disabled by connecting this pin to V
Serial data output pin for instructions as well as test and programming data. Data
is shifted out on the falling edge of
shifted out of the device. If the JTAG interface is not required on the board, the
JTAG circuitry can be disabled by leaving this pin unconnected.
Ω
IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices
chapter in the Cyclone III Device Handbook.
Jam Programming and Testing Language Specification
). The TDO output pin is powered by V
You cannot use the Cyclone III decompression feature if you are
configuring your Cyclone III device when using JTAG-based
configuration.
The TDO output is powered by the V
bank 1. For recommendations on how to connect a JTAG chain
with multiple voltages across the devices in the chain, refer to
the IEEE 1149.1 (JTAG) Boundary Scan Testing for Cyclone III
Devices chapter in the Cyclone III Device Handbook.
Table 10–14
explains each JTAG pin’s function.
TCK
Description
TCK
. If the JTAG interface is not required on the
Cyclone III Device Handbook, Volume 1
. The pin is tri-stated if data is not being
CCIO
pin. All the JTAG pins support
CCIO
CCIO
in I/O bank 1. All of the
power supply of I/O
JTAG Configuration
CC
.
10–71