EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 64

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Memory Blocks in Cyclone III Devices
Memory Modes
4–10
Cyclone III Device Handbook, Volume 1
The Cyclone III M9K memory blocks allow you to implement fully
synchronous SRAM memory in multiple modes of operation. Cyclone III
M9K memory does not support asynchronous (unregistered) memory
inputs.
The M9K memory blocks support the following modes:
■
■
■
■
■
■
1
Single-Port Mode
Single-port mode supports non-simultaneous read and write operations
from a single address.
configuration for Cyclone III memory blocks.
Figure 4–7. Single-Port Memory (1),
Notes to
(1)
(2)
During a write operation, behavior of the RAM outputs is configurable. If
you activate read enable during a write operation, RAM outputs will
show either the new data being written or the old data at that address. If
you perform a write operation with read enable deactivated, the RAM
outputs retain the values they held during the most recent active read
enable. To choose the desired behavior, set the Read-During-Write option
Single-port
Simple dual-port
True dual-port
Shift-register
ROM
FIFO
You can implement two single-port memory blocks in a single M9K block.
See
“Packed Mode Support”
Figure
Violating the setup or hold time on the memory block input
registers could corrupt memory contents. This applies to both
read and write operations.
4–7:
data[ ]
address[ ]
wren
byteena[]
addressstall
inclocken
rden
aclr
inclock
Figure 4–7
for more details.
shows the single-port memory
(2)
Altera Corporation-Preliminary
outclocken
outclock
q[]
March 2007