EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 302

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Configuring Cyclone III Devices
Figure 10–21. Multi-Device FPP Configuration Using an External Host
Notes to
(1)
(2)
(3)
(4)
(5)
10–66
Cyclone III Device Handbook, Volume 1
(MAX II Device or
Microprocessor)
External Host
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. V
Connect the pull-up resistor to the V
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
refer to
All I/O inputs must maintain a maximum AC voltage of 4.1 V. The DATA[7..0] and DCLK has to fit the maximum
overshoot equation outlined in
ADDR
Figure
Memory
Table 10–12 on page
CC
DATA[7..0]
should be high enough to meet the V
10–21:
10kΩ
V
CCIO
1
In multi-device FPP configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to the nCE pin of the next device
in the chain. The last device’s nCE input comes from the previous device,
while its nCEO pin is left floating. After the first device completes
configuration in a multi-device configuration chain, its nCEO pin drives
low to activate the second device’s nCE pin, which prompts the second
device to begin configuration. The second device in the chain begins
configuration within one clock cycle; therefore, the transfer of data
destinations is transparent to the MAX II device. All other configuration
pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are
connected to every device in the chain. The configuration signals may
require buffering to ensure signal integrity and prevent clock skew
(1) V
10–61. Connect the MSEL pins directly to V
10kΩ
“Configuration and JTAG Pin I/O Requirements” on page
CCIO
GND
CCIO
All I/O inputs must maintain a maximum AC voltage of 4.1 V.
In multi-device FPP configuration, the DATA[7..0] and DCLK
has to fit the maximum overshoot equation outlined in
“Configuration and JTAG Pin I/O Requirements” on
page
Cyclone III master and slave device(s) for DATA[7..0] and
DCLK.
(1)
Buffers (5)
supply voltage of I/O bank that the nCEO pin resides in.
10–13. You must connect the repeater buffers between the
Cyclone III Device 1
CONF_DONE
DATA[7..0] (5)
nCONFIG
DCLK (5)
nSTATUS
nCE
IH
specification of the I/O on the device and the external host.
MSEL[3..0]
nCEO
(4)
CCIO
V
CCIO (2)
or ground.
10kΩ
Altera Corporation-Preliminary
Cyclone III Device 2
CONF_DONE
nSTATUS
nCE
DATA[7..0] (5)
nCONFIG
DCLK (5)
10–13.
MSEL[3..0]
nCEO
March 2007
N.C. (3)
(4)