EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 444

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

I/O Timing
Figure 1–4. I/O Interface with Single External Output Resistor
1–34
Cyclone III Handbook
Differential Outputs
The Quartus II software reports the timing with the conditions shown in
Table 1–41
circuit that is represented by the output timing of the Quartus II software.
Figure 1–3. Output Delay Timing Reporting Setup Modeled by Quartus II (1),
(2)
Notes to
(1)
(2)
Figure 1–4
multiple external output resistors.
R
P
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
V
CCINT
Output
Buffer
Figure
V
GND
CCIO
is 1.10 V unless otherwise specified.
using the above equation.
and
1–3:
Figure 1–5
Output
Z = 50 Ω
Z = 50 Ω
V
MEAS
show the I/O interface with single and
R
S
GND
V
TT
R
C
Figure 1–3
T
L
Altera Corporation- Preliminary
R
shows the model of the
D
Differential Inputs
Output
Output
p
n
March 2007
R
D