EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 195
EP3C16F256I7N
Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
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Cyclone III
High-Speed
I/O Interface
Altera Corporation-Preliminary
March 2007
EP3C5
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
Table 8–2. Cyclone III Device Differential Channels (Part 1 of 2) (1),
Device
Package
EQFP
FBGA
EQFP
FBGA
EQFP
EQFP
FBGA
FBGA
EQFP
EQFP
FBGA
FBGA
EQFP
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
Cyclone III devices provide a multi-protocol interface that allows
communication between a variety of I/O standards, including LVDS,
RSDS, mini-LVDS, PPDS, LVPECL, differential HSTL, and differential
SSTL. This feature makes the Cyclone III device family ideal for
applications that require multiple I/O standards, such as protocol
translation.
You can use I/O pins and internal logic to implement a high-speed I/O
receiver and transmitter in Cyclone III devices. Cyclone III devices do not
contain dedicated serialization or deserialization circuitry. Therefore,
shift registers, internal phase-locked loops (PLLs), and I/O cells are used
to perform serial-to-parallel conversions on incoming data and parallel-
to-serial conversion on outgoing data.
Table 8–2
shows the numbers of Cyclone III device differential channels.
Pin Count
144
144
144
240
144
240
240
256
256
256
484
256
324
324
484
780
484
780
484
780
User I/O
128
115
215
123
151
101
169
Cyclone III Device Handbook, Volume 1
16
62
16
62
35
43
31
42
71
14
49
7
6
Cyclone III High-Speed I/O Interface
(2)
Number of Differential Channels
Clock Pin
4
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8–5
Total
136
123
223
131
159
109
177
20
66
20
66
15
43
51
14
39
50
79
22
57
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