EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 279

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 10–12. AP Configuration With Multiple Bus Masters
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Altera Corporation-Preliminary
March 2007
Connect the pull-up resistors to V
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed another device’s nCE pin.
The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
refer to
The current implementation for AP configuration ignores the RDY pin. However it is recommended that you connect
this pin.
When cascading Cyclone III devices in a multi-device AP configuration, connect the repeater buffers between the
Cyclone III master and slave device(s) for DATA[15..0] and DCLK. All I/O inputs must maintain a maximum AC
voltage of 4.1 V. The output resistance of the repeater buffers has to fit the maximum overshoot equation outlined
in
The other master device has to fit the maximum overshoot equation outlined in
Requirements” on page
The other master device can pulse nCONFIG if it is under system control rather than tied to V
“Configuration and JTAG Pin I/O Requirements” on page
Figure
Table 10–8 on page
Spansion S29WS-N Flash
10–12:
Intel P30 Flash/
RST#/RESET#
A[24:1]/A[23:0]
ADV#/AVD#
10–13.
WAIT/RDY
DQ[15:0]
Estimating AP Configuration Time
Active parallel configuration time is dominated by the time it takes to
transfer data from the parallel flash to the Cyclone III device. This parallel
interface is clocked by the Cyclone III DCLK output (generated from an
internal oscillator). As listed in
minimum frequency when using the 40-MHz oscillator is 20MHz (50 ns).
In the word-wide cascade programming, the DATA[15..0] bus transfers
a 16-bit word and essentially cuts configuration time to approximately
10–30. Connect the MSEL pins directly to V
WE#
OE#
CLK
CE#
CCIO
supply of the bank the pin resides in.
Other Master Device
Active Parallel Configuration (Supported Flash Memories)
(7)
10kΩ
10–13.
GND
Table 10–7 on page
10kΩ
V
Cyclone III Device Handbook, Volume 1
CCIO
Cyclone III Master Device
CCIO
nCE
DCLK (5)
nRESET
FLASH_nCE
nOE
nAVD
nWE
RDY (4)
DATA[15..0] (5)
PADD[23..0]
(1)
or GND.
10kΩ
V
CCIO
“Configuration and JTAG Pin I/O
(1)
MSEL[3..0]
10kΩ
V
nCEO
CCIO
10–17, the DCLK
(1)
CCIO
.
(2)
(3)
10–43